In Monday’s Electrical ad hoc I proposed two alternative solutions to resolving the Pattern Generator Characteristics table TBDs (see snapshot of slide below).
These tables define the pattern generator jitter used in the Host & Module stressed input test procedures.
The first proposal uses a CAUI-4 C2M like definition of pattern generator jitter.
The second proposal uses CDAUI-8 C2C TP0a like definition of pattern generator (clock) jitter. CEI-56-VSR-PAM4 uses such a definition.
- Although I have called out the 94.3.12.6.1 measurement method, the intention is “use CDAUI-8 C2C measurement method”.
The scope of this straw poll is not the specific table values, just the definition method:
Electrical ad hoc Straw Poll
I support a CAUI-4 C2M like definition of pattern generator jitter for the Host & Module stressed input test procedures ____
I support a CDAUI-8 C2C TP0a like definition of pattern generator (clock) jitter for the Host & Module stressed input test procedures __X__
Please respond by EOD Sunday so I can present the results at Monday’s electrical ad hoc.
Regards
Andre Szczepanek (P802.3bs 400 Gb/s Ethernet Task Force Electrical Ad Hoc chair)
