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Thanks. Yair From: Alan Flatman [mailto:a_flatman@xxxxxxxxxxxxx]
Yair, The ISO/IEC 11801 channel DC loop resistance requirements are for the temperature the cabling is designed to be used. ISO/IEC SC25 WG3 did worst case calculations some time ago to verify that this was practical. I have copied the relevant DC loop resistance and DC resistance unbalance requirements from ISO/IEC 11801 for reference (these are attached). Best regards, Alan On 29 Apr 2014, at 12:19, "Darshan, Yair" <YDarshan@xxxxxxxxxxxxx> wrote:
Thanks Alan, I see that also here the parameters are defined at 20degC and information is supplied for shorter channels at higher temperatures than 20degC for insertion
loss. Do you have information regarding loop resistance of channel and channel components, I guess it is specified at 20degC etc. as well. How the standard addresses
temperature higher or lower on this parameter? Thanks Yair From: Alan
Flatman [mailto:a_flatman@xxxxxxxxxxxxx] All, Please note that the channel length derating specified by ISO/IEC 11801 is slightly different for UTP in the temp range 40-60deg.C. Copy attached. Best regards, Alan Flatman On 29 Apr 2014, at 01:14, George Zimmerman <george@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote: You may wish to see ANSI/TIA 568-C.2 Annex G for channel length derating at elevated temperature. George Zimmerman CME Consulting, Inc. Experts in Advanced PHYsical Communications Technology 310-920-3860
Jeff, Can you point on reference showing that channel resistance at 100m specified at 50C? You may check if you are correct by calculating the resistance at for the cable we use for Type 2 if you are near 25 ohms round loop excluding 4 connector total
0.8 ohms. Yair From: Jeff
Heath [mailto:jheath@linear.com] All, I believe that this Ad-hoc should report the worst case cable imbalance at the temperature that creates the worst case condition, and is within the operating
range for the ‘channel’. In this case our analysis is including components beyond the PI because we seem collectively to feel it is prudent to do so. I believe that there is president for worst case analysis including temperature in previous PoE Task Forces. For instance, correct me if I am wrong here but
the worst case channel resistance at 100m is specified not at 25C, but rather at a hot ‘edge’ (was it 50C ambient plus cable heating?) In order to guarantee operability between PSEs and PDs, we needed to choose the worst case resistance of the channel. If
we want to interoperate, the same principle seems to apply here in my opinion. I believe that some of the pushback on this issue is perhaps because the worst case imbalance is dominated by the PD diode bridges. These components are indeed
not in the PI but we are considering them in this Ad-hoc none the less because they are material to cable imbalance. Interoperability is a key goal for this and any dot3 standard. I am open to other approaches in achieving this goal as long as it creates confidence in the Task
Force and dot3 that component providers and OEMs will understand what they need to do and systems will interoperate. Regards,
LINEAR TECHNOLOGY CORPORATION From: Darshan,
Yair [mailto:YDarshan@xxxxxxxxxxxxx] Hi all, Please review if I missed your name in the list of attendees on last Thursday a-hoc meeting. Thanks Yair ----
§ David
Tremblay / HP ------ Darshan Yair Chief R&D Engineer Analog Mixed Signal Group Microsemi Corporation 1 Hanagar St., P.O. Box 7220 Cell: +972-54-4893019 E-mail: <mailto:ydarshan@xxxxxxxxxxxxx>. |