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Hi Wayne,
Wayne I agree that we shouldn't be worried about.
The question is how to convert "don’t worry it is unrealistic in real installations" to "don’t worry, the spec says A, B, C" therefore don’t worry.
I am looking for some text/other means to close this hole in the future spec so if someone during tests will have "unrealistic channel" that is used in the lab and not in real life installation I can point him to the spec and say
"this is wrong setup ..and this is why, see the spec." .
I am working on such closure.
Yair From: Larsen, Wayne [mailto:WLARSEN@xxxxxxxxxxxxx]
My opinion would be that the unrealistic use cases do not need to be worried about. From: Darshan, Yair [mailto:YDarshan@xxxxxxxxxxxxx]
Hi Wayne, This solution, filters the "unrealistic use cases" that were resulted from short cables. How it helps? If we set a limit for the channel for 7%, and a user did use cabling and connectors combinations that is considered "not typical use case" or even "not realistic use case" and he got 12% it will be an issue for
him. The spec says A and he got B. This filters all the results of B which are not relevant to him when the channel is tested as standalone part. The justification for this approach is, when the channel is connected to a system, and the channel uses short cables, the End to End current/resistance unbalance will be dominant since their unbalance is higher
than the channel. This is one of the solutions from the table. There is 5th solution that in after our adhoc meeting Sterling and I were discussing and I am working on its details. Regards Yair From: Larsen, Wayne [mailto:WLARSEN@xxxxxxxxxxxxx]
Hi Yair, You showed a spreadsheet of four possible solutions, and one of them was to measure the DC resistance unbalance of the cabling channel with resistors in series with it.
What is the problem these solutions are solving? Wayne 7/2/14 From: Darshan, Yair [mailto:YDarshan@xxxxxxxxxxxxx]
H Wayne, Your question Is not clear to me can you elaborate? Yair From: Larsen, Wayne [mailto:WLARSEN@xxxxxxxxxxxxx]
Hi Yair, I was trying to ask, what problem is being solved by this? Wayne 7/2/14 From: Jeff Heath [mailto:jheath@xxxxxxxxxx]
Please announce when and why the ‘formal meeting’ has ended in the future. Regards,
From: Darshan, Yair [mailto:YDarshan@xxxxxxxxxxxxx]
I meant that we continue to discuss after the time of the forma meeting. The formal meeting ends when there is not sufficient attendees or someone ask to finish on time, or most of the group agrees to continue,
so after that time we can continue discussion whit out having decisions. Yair From: Jeff Heath [mailto:jheath@xxxxxxxxxx]
What do you mean by formal ad hoc meeting? Regards,
From: Darshan, Yair [mailto:YDarshan@xxxxxxxxxxxxx]
Thanks Jeff. I am working on this direction too and few others that we discuss after the formal 1 hour time of the adhoc meeting. Yair From: Jeff Heath [mailto:jheath@xxxxxxxxxx]
Yair, The entire principle of adding balanced resistance to test imbalanced channel resistance does not represent any real system. PSE PI and PD PI will add imbalance in worst case
analysis. At the end of the day only full worst case analysis using all three components will give us the correct worst case maximum current Regards,
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