Re: [802.3_4PPOE] PSE state machine - Stuck in ENTRY_SEC and related issues.

[Yair Darshan <YDarshan@xxxxxxxxxxxxx>]

Hi Chris,

 

1. I saw that this was the intent of the state machine in CC_DET_SEQ but you can get it and not limit it to only this case since “staggered” as originally presented by me during the 4PID adhoc doesn’t limited to do secondary detection when primary is ON.
2. You can do staggered detection also right after primary detection is done. ACTUALLY, this option for staggered is the most popular for e.g. doing connection check and/or detection. The use of the “staggered detection” as currently in the state machine is only useful when you don’t want to find the 4PID by 3 class events. If you do want to find 4PID capable by doing 3 class events, the current state machine prevents it from you when you are using CC_DET_SEQ=3 and there is no justification for it.
3. My point is that in all CC_DET_SEQ that allows staggered detection, we need to allow it for all the possible range of staggered detection. There is no technical reason why not to do it.
4. This can be corrected easily per darshan_13_0917.pdf page 5-6 with comment i-254.

 

5. I believe the question Lennart ask is much wider. Please see full discussion in darshan_13_0917.pdf page 5-6.

“parallel detection” is not well specified and the same “staggered detection”

 

I believe that this deserves a phone conference before meeting to save time.

 

Regards

 

Yair

 

From: Chris Bullock (bullock) [mailto:bullock@xxxxxxxxx]
Sent: Friday, September 1, 2017 7:09 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] PSE state machine - Stuck in ENTRY_SEC and related issues.

 

EXTERNAL EMAIL

Hi Lennart,

 

For DS, Sequence 3 enforces that detection on secondary pairset does not occur until after the primary pairset is powered.  That is what is meant by “staggered”.  For DS, Sequence 0, the detection/class has no enforced timing relationship.  “Parallel” just means that they happen pseudo-concurrently, but not necessarily sync’d.

 

Thanks,

Chris

 

 

From: Lennart Yseboodt [mailto:lennartyseboodt@xxxxxxxxx]
Sent: Friday, September 01, 2017 4:04 AM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] PSE state machine - Stuck in ENTRY_SEC and related issues.

 

Hi all,

Question to the folks who came up with the various CC_DET_SEQs.... what was the design intent of sequence 3 ?

I have the feeling there is a difference in interpretation of what is meant by "staggered" and "parallel".

For sequence 0, it is stated that "Connection Check is followed by staggered detection for a single-signature PD and parallel detection for a dual-signature PD."

Does 'parallel detection' imply that the detection has to happen precisely at the same time ?

Or can you do detect on pri, then detect on sec, and then proceed to classification ?

I would assert that the latter behavior is allowed by the state diagram.

Even if do_detect_pri and do_detect_sec are called at the same time, nothing forbids one of these functions to wait a bit until the other is done.

 

Kind regards,

Lennart

 

On Fri, Sep 1, 2017 at 3:10 AM, Heath Stewart <00000855853231d4-dmarc-request@xxxxxxxx> wrote:

Yair,

 

Thanks for your presentation. There are some interesting issues you identify in comments 251 and 252. We have reflected on your proposal and have created a proposal to address these issues.

 

Thanks,

 

-Heath Stewart

 

 

On Thu, Aug 31, 2017 at 3:12 AM, Yair Darshan <YDarshan@xxxxxxxxxxxxx> wrote:

Hi all,

Please review the remedy for this topic.

 

It handles the following:

1)      Preventing to be stuck in ENTRY_SEC when detection in primary has failed or tdet_timer_pri is done when transitioning from ENTRY_SEC to

START_DETECT_SEC.

2)      The transition from IDLE_SEC to START_DETECT_SEC when CC_DET_SEQ=3 is not fully covered for the staggered detection timing range.

3)      Both (1and 2) prevents doing cycles of detection and classifications until host decides to power on the port.

 

I’ll appreciate your inputs.

Regards

 

Yair

 

Darshan Yair

Chief R&D Engineer

Analog Mixed Signal Group

Microsemi Corporation

 

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E-mail: <mailto:ydarshan@xxxxxxxxxxxxx>.  

 

 

 

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