Hi Lennart,
I respond only to what you said.
And you are responding now to things that I didn’t say.
You said:
“I checked if this schottky leakage can cause issues with detection.
Attached are measurements of two devices:
- an active bridge controller with 8*NMOS. These transistors turn on above 30V, thus during detection the body diodes serve as the rectifier
- a schottky diode bridge
Three measurements are performed:
- true 2-pair
- 3-pair (2xpositive + 1x negative)
- 3-pair + 45K on the idle mode
Result: detection behaves the same in all cases”
I said:
Your conclusion that “detection behaves the same in all cases” means nothing in the 3rd test which is having 45K in parallel Rsig under 3-pair. And you and Chad can’t draw conclusions out of it that all is good.
Why?
-If it passes detection it could also be failed. It depends PD min Rsig value and the lower range of PSE valid/invalid threshold.
That is why this test proves nothing. If you do the correct worst-case test you will prove that it will be fail as expected to be i.e. detection will be polluted.
-Regarding what Joris showed, I will address it in separate mail in details. What he showed in short, doesn’t affect in any way what I have said above. If PD has leakage with Shotkey diodes with 100K load is less of a problem for meeting
detection for PD than connected to 45K.
Other claims of yours:
-I didn’t talk at all about connecting both negative so it is not clear to me why you address it at all?
See more below.
Yair
From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Wednesday, May 16, 2018 2:28 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] Backfeed ad hoc - 3P detection
EXTERNAL EMAIL
We will make more progress if you actually read & respond to what I said, rather than responding to stuff I definitely didn't say.
Yair: I fully agree and it works for both sides.
So let me summarize it again:
- Joris has made measurements that show that under 3-pair condition a schottky bridge leaks much more than under 2-pair condition
Yair: I will check it however, PD has to show valid sig in all operating modes. 2pair mode includes 3-pair mode according to table 145-20. So I don’t see a problem here. The fact that legacy PDs was designed to meet
all requirements under pure 2-pair is correct and it doesn’t change the fact that PD still need to meet all requirements for detection and classification under 3-pair. In other words, PD has to handle this.
- This has been confirmed by both myself and Shiyong (factor 100-500x higher leakage current)
Yair: As I said, I will check it.
- A test of 3 bridges is statistically insignificant,
[Yair: Correct]however we can conclude that it is possible to both fail or succeed the 2.8V/100K test with schottky's
Yair: Here is the thing: Failing the 2.8V and 28uA has nothing to do with the pollution of detection and classification. These are two orthogonal problems that when we bring the two to the extreme worstcase condition
may be converged to one case.
Which means if you meet 2.8V/28uA for sure you will not pollute detection and classification because in this case in series to the 45K you will have 2MEG.
Even if you have 10 times more current, you will have 200K in series to the 45K in which detection will not be affected and also Iclass.
I will check for higher rates too.
I have to say that you have to do many tests at worst case conditions to show that there is no problems and you are not there yet. Ob the other hand I show you one use case that fails detection and it is enough to
disqualify your approach.
In the test below I wanted to see what the effect was on the detection resistance curve under 3 conditions.
The result is that for the two devices I tested there is no difference in measured effective resistance.
What this tells us is that, even with higher leakage, the bridge blocks reverse current to the degree that it does not affect detection.
Yair: Yair; This is expected. Detection still stays valid. I am not surprised since I did the correct model and correct simulations.
Please see details in darshan_01_0518Rev006 annex B page 22. You can see that there us 1.8MEG minimum in series to the 45K on ALT B when we have a source of 57V and 28uA current limit. Now if you will use diodes
with more leakage you will still be OK until TBD leakage that will cause detection to be polluted.
A bridge that would connect the negatives together in detection, (which I did not test, because I have no such device), would indeed show a much lower detection resistance if there is 45K in the PSE.
Nobody is suggesting we allow bridges to connect the negatives in the detection range.
But that has nothing at all to do with my email below.
Yair: Why you mention this. It is not relevant to our discussion? I didn’t address it at all.
For the 10V vs 21V thing, please see Dave Abramsons slides that show that an Irev of 0.5mA does not cause a reduction in the classification current margins for PSEs.
Yair: I saw it and I disagree with it since it is not the root cause of the problem.
The issue is that PDs Iclass accuracy is marginal. If you add on top of it 0.5mA it worsen the problem. On the other hand the 1mA gap is used by the PSE in order to extend the range of valid class current. Now together
with the PD side, you narrow it by 18%.
I will address this in detail.
On Wed, 2018-05-16 at 09:23 +0000, Yair Darshan wrote:
Hi Lennart,
The 3rd use case which is our interest, doesn’t prove anything due to the following:
-in the PD you need to use the lowest possible value of Rsig.
-in the PSE ALT BE you have used 45K which is OK.
-In the PSE, there is no data for this specific PSE what is the range for pass/fail criteria so it doesn’t mean anything. PSEs has wide range of decision point to where to locate
the pass/fail criteria in which some PSEs will show valid signature result and some invalid result.
What is count is the worst case calculated condition:
If at the PD we have 25K*0.95=23.75K
And in parallel we have 45K, we will have 45K*23.75K/(45K+23.75K)=15.54K<19K which is invalid signature i.e. the detection was polluted.
So, it will happen! Your test doesn’t represent all worst case scenario from both sides the PSE and PD.
Yair
EXTERNAL EMAIL
I checked if this schottky leakage can cause issues with detection.
Attached are measurements of two devices:
- an active bridge controller with 8*NMOS. These transistors turn on above 30V, thus during detection the body diodes serve as the rectifier
- a schottky diode bridge
Three measurements are performed:
- 3-pair (2xpositive + 1x negative)
- 3-pair + 45K on the idle mode
Result: detection behaves the same in all cases
On Mon, 2018-05-14 at 21:33 +0000, Joris Lemahieu wrote:
Hi all,
please find attached my updated presentation from today.
Note that the 3P reflected voltage at 10V is larger than the 2P backfeed voltage at 57V (see measurements).
That would indicate that the new 3P reflected voltage requirement (even) at 10.1V would be harder to meet than the current 2P backfeed voltage at 57V.
Why then even push this further to 20.5V and still holding on to the very low 2.8Vrefl threshold.
You can never convince me that +0.028mA is the very critical threshold for classification to work under 3P.
For class signature 0/1/2 the PD current can change ±1.5mA from nominal and at the PSE side it can even change ±2.5mA from nominal.
Existing (single-signature) Type1 and Type2 PD’s were never designed to support 3-pair detection and 3-pair classification, only real 2-pair.
Some of those T1, T2 PD’s will already turn on their bottom mosfet even in the detection range if supplied by 3-pair.
For the success of the 3bt standard, it is important 4-pair capable PSE can successfully detect and classify as many ‘unexpected’ PD implementations as possible.
Now it seems like all PSEs will suffer and that PSEs are not able to act anymore. This is not the case.
If the 4-pair capable PSE can switch the positive pair, there will not be an issue during detection and classification.
If the PSE detection circuit is restricted to the first quadrant (due to series diode D2 in figure 145-20), there will not be an issue during detection and classification even if the PD would reflect the full
PD voltage.
There are still things a 4-pair cable PSE that does not switch the positive pair and that does not have series diode D2 could do to keep the margin on the classification current even if the PD would reflect the
full PD voltage:
-
the PSE detection source can be disabled (made Hi-Z) on the secondary alternative.
Nowhere in the 145B.1 CC_DET_SEQ timing diagrams Det is active on the secondary
alternative when Class is active on the primary alternative !
-
the PSE could adjust the voltage of the voltage source on the secondary alternative.
If the PSE really wants to keep the additional current at (or below) +0.028mA during classification it could adjust the voltage source value on the secondary alternative to:
-
2.8V (or less) below the Vpse on the primary alternative for Zsource=100kOhm
-
1.26V (or less) below the Vpse on the primary alternative for Zsource=45kOhm
Best Regards,
Joris Lemahieu
Application Engineer
ON Semiconductor
+32 55 33 29 49
Hi Yair,
these measurements clearly indicate:
-
The backfeed voltage specification has always been a symmetrical 2P test
-
If the symmetrical 2P backfeed voltage is extended to an asymmetrical 3P reflected voltage, a larger threshold then 2.8V would need to be taken into account for higher operating voltages.
-
There is no such thing as a 28uA backfeed current requirement for resistances lower than 100kOhm.
-
A 4-pair capable PSE that does not switch the positive conductor of the other mode during detection will influence the detection of a single-signature PD.
Best Regards,
Joris Lemahieu
Application Engineer
ON Semiconductor
+32 55 33 29 49
Hi Joris,
What do you suggest as a result of these measurements?
Yair
EXTERNAL EMAIL
hopefully my e-mail is delivered correctly now with just the measurement slides …
Joris Lemahieu
Application Engineer
ON Semiconductor
Hi Lennart, all,
I’ve made some measurements as well.
As I already expected:
“When extending the existing ‘symmetrical’ backfeed voltage specification to an ‘asymmetrical’ 3P reflected voltage specification,
a significantly larger reflected voltage value can be expected even with PDs using real diode bridges.”
However, I was surprised to see how quickly it can become close to the existing symmetrical limit under 3-pair condition and potentially fail then.
See last two slides of my updated presentation.
Best Regards,
Joris Lemahieu
Application Engineer
ON Semiconductor
+32 55 33 29 49
I've made a measurement on a PD with a schottky diode bridge we have here.
The diode type is the Vishay 30BQ100, a 3A rated diode.
The reflected voltage under 3-pair condition is much higher (factor 100x to 500x) than under 2-pair condition.
The good news is that even under high-temperate conditions that bridge meets our backfeed spec, even under 3-pair conditions.
At no point do I measure a voltage higher than about 820mV.
But... if the intent of the backfeed spec was to limit the current to 28uA, that goes out the window.
With an Rload of 150 Ohms instead of 100K, we get 70uA at no load condition, and we go into 2mA+ currents at elevated temperature.
Specification wise we are OK because the requirement ONLY holds at 100KOhm load resistance.
On Mon, 2018-05-07 at 21:45 +0000, Joris Lemahieu wrote:
Hi all,
I believe we are on the right track with the updates represented in the ‘yseboodt_01_0518_backfeed_baseline’.
The only concern I still have is with a “3-Pair PSE” trying to detect a single-signature PD (just for a single port system).
I have the impression the (schottky) diode reverse leakage has not always been taken into account properly:
either just neglected or represented as being a resistor (without additional current source in parallel).
See my presentation in attachment.
My concern is that a PD with real (schottky) diode bridges might become non-compliant to the 3bt standard
and that a “3-Pair PSE” would be allowed not being able to detect a PDs with real (schottky) diode bridges anymore,
due to hard to meet leakage current requirements.
As such I do not have any problem with that, but do we really want to go that far?
Next to my presentation, I also attached a spice schematic file for those that would like make simulations.
FYI, the name “3-Pair PSE” is short for
“a 4-pair capable PSE providing power in 2-pair mode, whereby two pairs are connected to the positive VPSE, and one pair is connected to
the negative VPSE“.
Best Regards,
Joris Lemahieu
Application Engineer
ON Semiconductor
+32 55 33 29 49
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