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Re: [802.3_4PPOE] Classification Margin Slides- Review of David Abramson presentation by Yair

Hi David,

Many thanks for this work.

It allows me to show, that we are missing the point that some of us are trying to make. Please see details in the file attached.

 

Short summary of my inputs:

The issue is not the 1mA margin between the PSE and PD requirements.

The problem is; In the example, you took (and problem is the same for any class we will take) the PSE put its threshold for deciding Class 0 or Class 1 at 6.5mA.

If PD will use the normal Iclass, the margin between this PSE threshold to the maximum class 0 current will be (6.5-4)=2.5mA. This is +/-38.46% margin.  

Now if we allow 0.5mA more to Iclass, the margin will be reduced to 30.77%. This means that legacy PDs that worked well with legacy PSEs, now may fail to show the correct Iclass with Type 3 and 4 PSEs operating in 3-pair mode. This is interoperability issue.  

The problem gets worse if we allow 1.3mA. In this case the margin drops to 18.46% only.

 

See more for some of the assumptions you have used which are incorrect and some are correct but doesn’t change the above problem.

 

So, obviously the 0.5mA reduces the magnitude of the problem but still it is major interoperability problem also with 0.5mA too.

 

I’ll appreciate your response.

 

Yair

 

 

From: Abramson, David [mailto:000009c91bbcc8ad-dmarc-request@xxxxxxxx]
Sent: Monday, May 14, 2018 11:50 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: [802.3_4PPOE] Classification Margin Slides

 

EXTERNAL EMAIL

Hi everyone,

 

I put together a few slides with some thoughts about classification margin and some other ideas.  They are attached.

 

Regards,

 

David Abramson

IC Design

Power Interface

Texas Instruments

Office:  603.222.8519

Mobile:  603.410.7884

 

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Attachment: Classification_Margin_WITH_YAIR_REVIEW.PDF
Description: Classification_Margin_WITH_YAIR_REVIEW.PDF