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Mark, As I said, not sure new objectives are needed at all. However, after the discussions I had with Matt, I can see how that might happen – and if it does then we can address it then. John From: Mark Nowell (mnowell) [mailto:mnowell@xxxxxxxxx] John, You bring up a good point and one that was in my mind when I was raising my questions on this week’s ad hoc but that I didn’t articulate. My concern was with our potential SG schedule of getting Working Group approval in March to move to Task Force and seeing an incomplete proposal tying us up in knots and risking the schedule. The email thread confirms my concern. The reason I’m jumping in on this was to encourage a complete proposal to happen asap. But, you are right, this is an issue that can be pushed into Task Force and perhaps should be. We will need to add objectives if we head in this direction and those are within the ownership of the Working Group alone. I do not think the current objectives and CSD responses would be insufficient without this topic being resolved. Caveat – that the current objectives are insufficient on the copper objectives and we DO need to get those resolved in March if we hope to move forward, but that is a different topic. Mark On 2/25/16, 11:01 AM, "John D'Ambrosia" <jdambrosia@xxxxxxxxx> wrote: Mark, This is raising a very important issue that I think people are now raising very good questions about and this topic I think requires further discussion. I believe a main assumption for many of us has been that 50Gb/s signaling will be PAM-4. However, as an industry, we also made a decision to enable 25Gb/s NRZ signaling. As a point of reference, I talked to Dale Murray from LightCounting, and he informed me that over half the Ethernet optics shipped are for 10G that use serial 10G interfaces. The point to that reference is that 10G electrical interfaces are still clearly being used, even though we now have faster solutions. Therefore, it would seem a very reasonable assumption that 25Gb/s based NRZ will be out in the market for some time. In my gut, it just feels like we will limit broad market potential by forcing people to have to develop new 50G PAM4 I/O to be used everywhere to enable 50G/200G implementations. Therefore, I am pretty confident it will happen somehow, which will then cause us other interoperability issues to worry about. I was going to write more on the LAUI-2, but after a very informative discussion with Matt Brown, it is more clear to me that much of this discussion is better served in the TF. I don’t fully agree with your assessment on the need for new PHY objectives yet. And I would need some powerful persuasion to understand how distinct identity were being met if some of the conditions you described happened. It will depend on a lot of things that are better discussed in relation to baseline proposals. Not sure how you feel about this topic being punted into TF – as you know we haven’t seen eye-2-eye on whether this is in scope of a TF based on the current objectives, as currently defined. I believe it is, and people should be free to consider methods to enable a x2 based interface by trying to meet the physical layer specifications. And as a chair, I would always point out to people to fight the right battles at the right time. If we can agree that this is a Task Force discussion, then we can focus our energies on trying to move out of Study Group. John From: Mark Nowell (mnowell) [mailto:mnowell@xxxxxxxxx] Thanks Ali, I guess my main point is that if the new additional proposed AUIs result in there being a different data pattern or signal on the physical media (different FEC, different PCS architecture, or different bit rate) then it isn’t as simple as just adding that additional AUI in isolation. Your example of XSBI is consistent with this. We can add new AUIs in isolation as much as we want either in IEEE or in MSAs. We saw 10GBASE-R running over XSBI (16 lanes), XAUI (4 lanes), XFI (1 lane) and SFI (1 lane). But in all those cases the PCS was unchanged and the bits on the physical media where unchanged for a particular PHY through all those different AUIsso we had guaranteed interop, regardless of implementation. You can still connect a 10GE port using SFP modules and SFI AUI to a 10GE port using a 300 pin module and XSBI today (if you can find one). Since we seem to love trawling back through the spec to see how we did things in the past, I’d suggest looking at 10GE where we defined the XSBI. We had a backwards compatibility goal there with OC192 and handled that with the definition of the WIS layer (Cl 50). If you look at the 10GE introduction section table (Table 44-1) you can see where the WIS was included it was associated with unique PHYs (10GBASE-W) since the bits on the wire were different and wouldn’t interoperate with the other 10GBASE-R PHYs. Please be very clear, I’m not saying what you are proposing can’t be done. I’m just pointing out that from an IEEE perspective where our goal is to develop interoperable specs it is not as simple as just adding in an optional AUI in isolation and we therefore need to work through what needs to be done so the SG understands what is actually being asked of it. Mark On 2/24/16, 11:28 PM, "Ali Ghiasi" <aghiasi@xxxxxxxxx> wrote: Mark Thank you detail replay, please see my comments below inline, hopefully the inline will get through this time! Thanks, Ali Ghiasi On Feb 24, 2016, at 7:02 PM, Mark Nowell (mnowell) <mnowell@xxxxxxxxx> wrote:
As you stated CAUI-4 can operate without needing FEC protection but end to end FEC is enabled for 100GBase-SR4 operation. If 50 GbE PMD operates with RS(528,514) then there is no speed up. In case we need RS(544,514) for 50 GbE PMDs the PMA-PMA system interface can operate naked just as the case of CAUI-4 the PMA-PMA adds the RS(544,514) form bit/symbol mux.
There are already products in the market place as shown in SSCC2016 paper below with CAUI-4/50GAUI-2 to 2x50G/1x50G, the input bit rate is different than output bit rate and the device initiates FEC. 4. 3.4 A 40/50/100Gb/s PAM-4 Ethernet Transceiver in 28nm CMOS K. Gopalakrishnan1, A. Ren1, A. Tan1, A. Farhood1, A. Tiruvur1, B. Helal1, C-F. Loi2, C. Jiang1, H. Cirit1, I. Quek2, J. Riani1, J. Gorecki1, J. Wu1, J. Pernillo1, L. Tse1, 1Inphi, Santa Clara, CA; 2Inphi, Singapore, Singapore; 3Inphi, Irvine, CA
We have had presendance defining optional interfaces and not defining PMD for the optional AUI. XSBI (16 lane) which was the interface on the 300 pin MSA had no 16 lanes PMD associated. The largest application for 10 lanes 100 GbE was CAUI-10, even though we end up defining 10 lanes SR and CU.
I agree likely RS(544,514) but we need to perform the diligence during the study group.
If RS(544,514) FEC required for operation of new 100 GbE PMD in that case the CAUI-4 interface will operate naked then FEC will be initiated in the PMA-PMA (4:2) device. We know CAUI-4 can operate with BER 1E-15 so we can simplify the problem and assume RS(544,514) FEC is available for the 50G/lane PMD, in effect you can view CAUI-4 to CAUI-2 as logical interface. A logical PCS implementation will support 4/2 lanes so the question is wouldn’t be better that the AUI is defined in the IEEE instead of an MSA? Below is ISSCC2106 paper showing an implementation with 4:2 PMA mux with different input output rate and FEC initiation. 4. 3.4 A 40/50/100Gb/s PAM-4 Ethernet Transceiver in 28nm CMOS K. Gopalakrishnan1, A. Ren1, A. Tan1, A. Farhood1, A. Tiruvur1, B. Helal1, C-F. Loi2, C. Jiang1, H. Cirit1, I. Quek2, J. Riani1, J. Gorecki1, J. Wu1, J. Pernillo1, L. Tse1, 1Inphi, Santa Clara, CA; 2Inphi, Singapore, Singapore; 3Inphi, Irvine, CA
Thank you for suggestion and I will take look at the Table 80-2 to further refine the proposal.
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