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Dear Task Force Participants, During the 3/08, 3/29 and 5/17 2022 meetings, we started the debate between the two options for 800 GbE PCS/FEC/PMA, where option 1 was a 2X parallel CL119 and option 2 was a sped-up CL119, based on the following contributions: Option 1: https://www.ieee802.org/3/df/public/22_03/shrikhande_3df_01_220329.pdf https://www.ieee802.org/3/df/public/22_05/22_0517/shrikhande_3df_01a_220517.pdf Option 2: https://www.ieee802.org/3/df/public/22_03/wang_3df_01a_220308.pdf https://www.ieee802.org/3/df/public/22_05/22_0517/he_3df_01_220517.pdf I feel it is necessary to share our collected questions under discussion, and concerns raised in the meetings and hope to trigger further considerations when selecting from the two candidate options.
1.
Option 1 defines 4 FEC codewords operating in parallel. ANY 4 of the 32 PCS lanes can be muxed in the PMA to generate a 100Gb/s lane. From FEC error correction capability perspective, it is actually equivalent
to 2 FEC codeword interleave, but with the cost of additional 12.8ns latency, and associated area and power comparing to Option 2.
2.
The Clock Content issue is still open and further work is needed as mentioned in Slides 18 of “800GbE PCS/FEC/PMA Baseline Proposal for PHYs using 8 x 100G PMD lanes - Update”.
3.
Slides #12&13 of “Analysis of FEC1 Proposals from Reuse Perspective” reveals the FLR challenge with 4 FEC codeword in parallel as in option 1, based on current 802.3 definition. This will lead to 2X FLR observed
when validating a 800Gb/s module plugged into a host port when operating in 800GbE mode comparing to 400GbE mode.
Please keep in mind the BER Objective for the 802.3df project for 800 Gb/s is the same for 200 Gb/s, 400 Gb/s -
Support a BER of better than or equal to 10 -13 at the MAC/PLS service interface (or the frame loss ratio equivalent)
4.
Considering long term evolution with at least 10 years of life cycle of the standard, option 2 will benefit from advanced process and Moore’s Law. Implementation with option 2 can be more optimal. Both option 1 and 2 could support a fast time-market 800GbE @ 8X100 Gb/s per lane technology, as we are still at the early stage of the standard development. With either option adopted, the pace of D1.0/2.0/3.0 is similar.
Since the debate is likely to happen in the 5/24 meeting, I hope the information above is helpful. More analysis is expected to support the project goal.
Any feedback is appreciated. Thanks! Xinyuan 发件人: Wangxinyuan(Xinyuan) <>
Hi John, After going through the uploaded material, the “Analysis of FEC1 Proposals from Reuse Perspective ” by Xiang He and me as co-author address application for 800GE with 8X100G AUI and PMD, which
is same as “800GbE PCS/FEC/PMA Baseline Proposal for PHYs using 8 x 100G PMD lanes ? Update” So I suggest to reschedule the agenda to move the “Analysis of FEC1 Proposals from Reuse Perspective ” before my another contribution “Concatenated Code Update in PCS/FEC/PMA Architecture”.
I think this will help to discuss and understand for either this topic and the concatenated code. Thanks! Xinyuan 发件人: John D'Ambrosia <jdambrosia@xxxxxxxxx>
All, The meeting materials for the 17 May 2022 Teleconference Meeting have been uploaded -
https://www.ieee802.org/3/df/public/22_05/index.html. As you can see there is a substantial amount of material to cover. Therefore, I am informing everyone that we will begin the meeting promptly at 10am. Speakers have been informed that they will be held to their times for presentation,
and there will be a limited amount of time for questions of clarification, and there wont be time for debating with the presenter or prolonged pontification. Time for discussion / straw polls / motions has been allocated on the 24 May meeting. Your support in using our meeting time effectively is appreciated. Regards, John D’Ambrosia Chair, IEEE P802.3df Task Force To unsubscribe from the STDS-802-3-B400G list, click the following link:
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