And I am suggesting you provide a contribution regarding acc if you wish to see it included in efforts. No one should assume any work they want to see done will be done. From: Chris Cole <chris@xxxxxxxxxxxxxxx>
Sent: Wednesday, September 28, 2022 2:10 PM
To: STDS-802-3-B400G@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_B400G] Oct 2022 Series Webpage Update Hi John, You may have missed Adee's original email, but he was asking about what investigations would be helpful to the TF, which then presumably would lead to a contribution(s). Closely hewing to your admonitions on today's call, I am suggesting to Adee that including ACC in the investigation is valuable. An in-depth study is a preferable precursor to a contribution, so that it has substance. Chris, I guess my message isn’t getting across. We have heard discussions about active cable assemblies, however, I still have not seen really any presentations, other than Kent providing a terminology basis. Given that there is no proposal for an active cable assembly – how do you know it is using an AUI? That point was actually raised and discussed. So let me be redundant – we are a contribution driven organization. You know the rest of the drill from there. John Hi Adee I am not sure what we will learn because you are compromising the "short AUI" solution. What is interesting is to compare two scenarios, each optimized around their AUI. - ~36dB ASIC SerDes
- VSR interface to module (full range of front pluggable PCB trace reaches)
- ~36dB module SerDes
- FEC terminated in optics module
- DAC
- ~20dB ASIC SerDes
- XSR interface to module (i.e. restricted to short reach PCB trace reaches, or cable over PCB, or NPO)
- ~20dB module SerDes
- end to end FEC
- ACC only (no DAC option)
Following today’s call and straw polls, I’m thinking of doing some analysis for the “lower loss” AUI. I can see the two specifications going in a few directions: - “Long AUI”: up to 36 dB with termination of the RS544 (DER≈1e-4); “Short AUI”: up to x dB without termination (DER≈1e-5). Essentially segmented/concatenated, but with the same bits on the optics for both. Electrical specs may be the same, except for the BER/DER parameter. This would enable modules with no RS-FEC implementation – lower area, power, AND latency.
- “Long AUI”: same as above; “Short AUI”: up to x dB with weaker SerDes assumptions (equalization etc.) but same DER target. Both assume termination of the RS-FEC. Different electrical specs. “low loss” modules can have lower power and area, but a relatively small effect on latency.
- A combination of the two above – if something can be gained (I’m not sure)
- Something else?
Is there a preferred direction? </Adee> Yes, if you have a wide loss dynamic range then of course calibration or training is critical. But the more important question is why have it in the first place. For many generations of copper interconnect, the loss was dominated by one segment of the channel. In that case, one large gain stage works just fine. But this is no longer the case. The packages at both ends, the PCB trace(s), the cable if there is one, all are significant contributors. Basic math tells us that a single large gain stage is a power inefficient solution to this problem. That's nothing new. Nearly two hundred years ago, people figured that when stringing telegraph lines they needed to intersperse them with repeaters. They didn't have the math to help them understand why. However, we do, so what's our excuse? A DAC at 224G/lane is not the lowest power solution; it's the highest power solution. To add insult to injury you and Gary want to force this overgrown gain on C2M channels that don't need it. Training or calibration hardly makes it palatable. Chris, I don’t need to have a self-driving car to get anti-lock brakes. The challenge here is calibration of control. A scheme that is robust to miscalibration is enabling. Jeff [External Email. Be cautious of content] That's a great idea. Swiss Army knife do-it-all engineering solutions have always resulted in lowest cost and power. In the same vein, we should adopt Coherent ZR for all optical PMD reaches. After all, it's powerful link training is fully capable of adapting to the worst case multi-hundred km channels, and all shorter applications down to tens of meters. Gary, I indeed hope it becomes mute. The discussion here was recalling that AUI was devised with two loss targets for 100G electrical lanes. We avoided detailed parameter programming. To embrace even more complex configuration, then link training indeed becomes attractive. Jeff [External Email. Be cautious of content] Does all of this become mute when we move to electrical link training for 200G C2M ? I thought the intent of link training is that rather than having a pre-defined set of parameters based on the worst-case channel (or in the case of 3ck the two worst channels of AUI-S and AUI-L), that the parameters are adapted to match the actual channel ? Gary Chris, I agree deeper thinking needed. How we indicate and configure AUI support is an important problem too or interop between host and module may never happen despite all the excellent deep thinking. Jeff [External Email. Be cautious of content] I am glad we have zeroed in on the critical aspect of what needs to be done. I was trying to distract us with side topics like the loss budget and applications scenarios, but perhaps that will just fall out of getting the correct host id. Ali, AUI-S and AUI-L are not PMDs in SFF-8024. They are Host Electrical Interface IDs. At present, they are seen as two configurations of one implementation. Please see IEEE 802.3ck, where they are defined as such. How do you see mapping “classes of AUIs” to Host Electrical Interface IDs? Jeff [External Email. Be cautious of content] Hello Jeff, AUI-S and AUI-L is are two settings for the same retime interface (4/5 taps FFE with RX CTLE+4DFE taps), assuming we will introduce some level of adaptive transmitter via CMIS-LT/CL136 you could have 1000’s of valid TX settings. It is unfortunate that in SFF-8024 AUI-S/L are defined as if they were different PMDs, they are just two settings for one PMD! AUI-I, II, III, and IV all are in my opinion within the scope of the 802.3df.
To unsubscribe from the STDS-802-3-B400G list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=STDS-802-3-B400G&A=1 I thought we already agreed to leverage IEEE 802.3ck. I was simply pointing out that we have for instance 100GAUI-1-S and 100GAUI-1-L from IEEE 802.3ck, which I understand we will similarly develop 800GAUI-8-S and 800GAUI-8-L. Juniper Business Use Only [External Email. Be cautious of content] At this point for 200g lanes - no decisions have been made. Perhaps there is progress elsewhere but that does not apply within our project. As always we are a contribution driven organization. John When we finish the first draft we will send it to you. We already have AUI-S and AUI-L for two ranges essentially of loss, not just one. Regardless, we do have more kinds of implementations needing support from the standard. Non-Juniper [External Email. Be cautious of content] Dear IEEE 802.3df Participants, I trust everyone rushed to review next week's material as soon as John announced its availability, and discovered the excellent exposition by Mr. Lusted. For those with limited time and trying to decide which presentation to read, may I kindly call your attention to: As always, Kent is gently steering us towards wisdom, which for some of us who prefer the more direct approach, is a bit too old school. What's clear is that a single large loss AUI C2M is no longer sufficient and we should write multiple specifications to adequately meet the need of mushrooming applications, specifically: - Traditional large loss for LR backplane, CR passive DAC, and VSR front pluggable
- New XSR for NPO, twinax-over-PCB, active copper, and XSR front pluggable
Obviously the exact loss is TBD, however a good start for the XSR value are the shorter reach examples in last year's presentation by Sam and Nathan. In off-line discussions, there has been a lot of interest in XSR's potential to save power, which we will direct into a proposal for the next meeting. For those that would like to join us in contributing or reviewing, please send me an email so that we can put you on copy as we iterate a draft. All, The webpage for the Oct 2022 Series has been updated with all presentation material for next week - https://www.ieee802.org/3/df/public/22_10/index.html. The proposed PAR modification to IEEE P802.3df and the proposed IEEE P02.3dj PAR have been uploaded. I wish to highlight the proposed PAR modification to IEEE P802.3df- https://www.ieee802.org/3/df/public/22_10/22_0927/PAR_P802p3df_Proposed_220927.pdf. As previously noted, I was working with Mr. Law on getting the PARs entered into the MyProject system. An issue has arisen that has not currently been resolved – For the proposed PAR modification to P802.3df, the date for Item 4.2 could not be entered as presented to the Task Force. The date proposed to the Task Force was Nov. 2023, however, the MyProject system will not permit entry of a date earlier than Jan 2024. Mr. Law has contacted IEEE SA Solutions Support regarding this issue. At this time the date of Jan 2024 has been entered for Item 4.2 with the following noted entered for 8.1 – Item 4.2: The earliest date that Myproject would allow to be entered is Jan 2024. This prevented the entry of the desired date of Nov 2023. (A bug report has been submitted to IEEE SA Solutions Support. This item of the PAR will be updated to the desired date of Nov 2023 and this note deleted immediately upon a solution being provided.) For the consideration of the Task Force - the motion to adopt this proposed PAR will be modified to allow modification of the PAR in accordance with the note above. Regards, John D’Ambrosia Chair, IEEE P802.3df Task Force
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