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Hello Max, thank you for sharing the slides with the group. Of some of the aspects you are showing, I have a fundamentally different understanding and therefore cannot follow your arguments or
conclusion. It looks to me that you are neglecting the difference between link and line rate and the levels in the processing chain at which the comparisons happen (i.e. at PHY or MAC level).
On slide 6, e.g. I do not understand why you set the TDD cycle to 125.3us. If you do that, you would not be able to achieve a 10G/100M (average) link rate any more. To ensure the same
throughput, a TDD system would always have a somewhat higher line rate (compared with a system with the same processing overhead, more in my latency presentation) and an FDD system would always occupy a higher frequency range. The link rate and what the MAC
sees, is unaffected. I do not understand, why you tie, what happens on PHY level to what happens at the MAC level. That seems unnecessary to me.
I see two ways of achieving asymmetric link rates (also somewhat addressed in the buffering presentation) between MAC and PHY ( I remember a presentation from William Lo also discussing
those).
So, for what reason would the MAC need to know the PHY timing?
In general: I see the solution, we are discussing at dm, for the last hop to the camera. Also, I do not see the TAS in cars, independent from the PHY. Maybe some of the different understandings
come from there? Kind regards,
Kirsten Von: Max Turner <max.turner@xxxxxxxx>
Dear all! Please find attached my slides for the .3dm session during the July Plenary. Feedback and questions up front are very welcome! Best Max
-- Max Turner, Dipl.Phys. Automotive
Network Architect Ethernovia BV Utrechtseweg 75 3702AA Zeist The Netherlands c-de: +49 177 863 7804 c-nl: +31 685 386 449 To unsubscribe from the STDS-802-3-ISAAC list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=STDS-802-3-ISAAC&A=1 |