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Ky-Anh Thanks for the question. I believe I did answer that question in the call, the comparison for power saving is for DSP active power. Please see page 11. “During active periods, the DSP power is also reduced by 95%”. Thanks Ahmad Sent from Mail for Windows From: Ky-Anh Tran Thank you Ahmad, Mehmet for the detailed power / complexity analysis. Related to alireza’s request, I was having a hard time understanding the assumptions lead to the 95% power saving calculation, slide 12 of: https://www.ieee802.org/3/dm/public/0724/Chini_Tazebay_3dm_01a_0724.pdf “Compared to P802.3ch EEE, up to 95% savings in complexity and power is expected using a ADC/DSP-based solution and even more savings using a CTLE+DFE for equalization”
From: Alireza Razavi <arazavimajom@xxxxxxxxxxx> Ahmad/Mehmet Thank you for your presentation. Could you provide more details about your assumptions for the materials in slide 11? Additionally, can your model or measurement compare the average and maximum power of the PHY on the camera side for EEE and time division mode? Furthermore, you compared two methods for the 2.5G/100M mode. How do these numbers change for the 10G/100M mode? Best Alireza To unsubscribe from the STDS-802-3-ISAAC list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=STDS-802-3-ISAAC&A=1 To unsubscribe from the STDS-802-3-ISAAC list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=STDS-802-3-ISAAC&A=1 To unsubscribe from the STDS-802-3-ISAAC list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=STDS-802-3-ISAAC&A=1 |