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Hi Max, I integrated your inputs and took a crack at rewriting Annex 201A in the attached.
I feel in your changes we left in figure 201A-1 but never referred to it. There were also terms used in your modification that were not defined. I feel that I addressed these issues while keeping to
the spirit of what you are doing. Let me know if this works for you. Thanks, William From: Max Turner <max.turner@xxxxxxxx>
Dear all! I'd want to take another stab at improving the wording around the PHY Delay in 201.14 and Annex 201A (as well as long term outside this project in 149.10). In 201.14 - Change the paragraphs on page 152 in lines 45 to 54 to read instead: "The HS_PATH delay is defined as the time needed for a given unit of data to traverse from the input at the PHY_S XGMII to its presentation at the PHY_D XGMII, minus the link segment propagation delay. The LS_PATH delay is defined as the time needed for a given unit of data to traverse from the input at the PHY_D XGMII to its presentation at the PHY_S XGMII, minus the link segment propagation delay. These delays shall not exceed the limits shown in Table 201–24." The above changes remove duplications and redundant terms (e.g. "data delay"). Add a plural "s" to PHY in line 18 of page 153. In Annex 201A - Delete the last sentence of the first paragraph on page 249 lines 9 and 10 (starting with "In asymmetrical ..."). As that wording does not add value. Furthermore change Annex 201A on pages 249 from line 12 and all of page 250 to read: " - The HS_PATH delay of 201.14 is composed of the HS_TX delay in the PHY_S (XGMII to MDI) and the HS_RX delay in the PHY_D (MDI to XGMII) . - The LS_PATH delay of 201.14 is composed of the LS_TX delay in the PHY_D (XGMII to MDI) and the LS_RX delay in the PHY_S (MDI to XGMII). Besides the MAC Control PAUSE operation (Clause 31, Annex 31B), also the time synchronization support (Clause 90) requires this information for best interoperability between different implementations. It is therefore recommended to allocate
the PATH delay portions as follows: a) The HS_TX delay is allocated 10% of the HS_PATH delay budget of Table 201-24. Due to potential interleaving only the XGMII transfer X(n) encoded into the first 64B/65B block of an RS-FEC superframe (identical to the RS-FEC frame for L=1, per 202.3.2.2.14) can practically be used to define the delay between XGMII
and MDI (or vice versa). As this is not accessible easily, it is recommended for the PHY implementers to specify TX delay and RX delay in the product's documentation and keep their variation low. " Keep Figure 201A-1! To me this is shorter, with less/simpler terms, but is easier to read/understand. Best Max
-- Max Turner, Dipl.Phys. Automotive
Network Architect Ethernovia BV Utrechtseweg 75 3702AA Zeist The Netherlands c-de: +49 177 863 7804 c-nl: +31 685 386 449 On Tue, Apr 7, 2026 at 6:34 PM George Zimmerman <george@xxxxxxxxxxxxxxxxxxxx> wrote:
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