Re: [802.3_ISAAC] Question abut Schedl_etal_3dm_01_0926.pdf

[Ragnar Jonsson <ragnar.jonsson@xxxxxxxxx>]

Hi Scott,

I have been reviewing the delay constraints in subclause 192.12 (Table 192-27). While looking at the proposed entries for the 1 Gb/s configurations, a few apparent arithmetic and budgeting discrepancies caught my attention.

Could you provide some additional background or share the rationale used to derive the current values for these new modes? Specifically, I am trying to reconcile two key areas:

1. Arithmetic consistency in the 7.5G+1000 row In Table 192-27, the row for 7.5G+1000 specifies:

• Maximum delay: 30,480 BT
• Maximum delay: 40 pause_quanta
• Maximum delay: 4,096 ns

Checking the standard conversions (1\text{ pause\_quantum} = 512\text{ BT}):

• 40\text{ pause\_quanta} \times 512\text{ BT/PQ} = 20,480\text{ BT}, which translates to 2,730.67\text{ ns} at 7.5 Gb/s rather than the listed 4,096 ns.
• Conversely, achieving 4,096 ns at 7.5 Gb/s requires 4,096\text{ ns} \times 7.5\text{ Gbps} = 30,720\text{ BT}, which resolves cleanly to exactly 60 pause_quanta (30,720 / 512 = 60).
• The listed 30,480 BT also appears slightly off from this target (30,480 / 7.5\text{ Gbps} = 4,064\text{ ns}).

It looks like the intent may have been 30,720 BT and 60 pause_quanta to match 4,096 ns—could you confirm if that was the case?

2. Physical implementation margin for 5G+1000 Looking at the physical lower bounds on latency across TDD cycles, moving the return path from 100 Mb/s to 1 Gb/s reduces the High-Speed transmit window from 8,693.33 ns down to 6,949.33 ns (to accommodate the larger LS burst). This expands the worst-case HS transmitter silent/buffer wait time by 1,744 ns (from 906.67 ns to 2,650.67 ns).

When factoring in the minimum RX FEC decode latency (L \times \text{codeword duration}):

• For 5G+100, the minimum physical latency is ~950 ns, leaving ~1,100 ns of implementation margin under the 2,048 ns limit.
• For 7.5G+1000, the minimum physical latency is ~2,715 ns, leaving ~1,380 ns of margin under the 4,096 ns limit.
• For 5G+1000, however, the minimum physical latency is ~2,694 ns. With the table currently setting the maximum delay to 3,072 ns, the available margin shrinks to only ~379 ns.

This provides barely a third of the implementation budget allowed for the other modes, which could make it difficult for standard digital pipelines, sync FIFOs, and clock domain crossings to achieve compliance using shared silicon architectures. If we applied the same ~1,100 ns margin used in 5G+100 (2,048\text{ ns} + 1,744\text{ ns} = 3,792\text{ ns}), a target around 4,096 ns (40 pause_quanta / 20,480 BT) would appear more aligned.

I would appreciate any insight into how the 3,072 ns ceiling was modeled or whether there were specific system-level constraints driving that number.

Best regards,
Ragnar

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