| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
|
Dear Natalie, Dear all, This objective is quiet unclear to me up to now and there are some points to consider: I guess your objective/requirement is from a system point of view (end-2-end latency, e.g. from a sensor to a computing unit) and for a dedicated amount of data (e.g. on picutre of a camera or one snapshot of a radar)? If so the latency you talk about is defined by a lot more elements than a .3 PHY: -
Time until data is present at the sensors PHY’s MAC-interface -
Time from MAC to MDI on sensors PHY (can be defined in .3) -
Time for transmission over link segment channel -
Time for the way of the data through every switch (and always from MDI->MAC, MAC->MDI and link segment channel) -
Time from MDI to MAC on compute ECU’s PHY/switch (can be defined in .3) -
Time until higher layers in compute ECU have received data Going through these points from layer 0 to higher layers and assuming we want to know how long one MTU Ethernet frame will need to go through the network we have the following: -
The speed of light is quiet fix, so the transmission of a bit over a 10m/15m link segment is quiete small: 15m / (2E8m/s) = 75ns
-
As said MAC-MDI and MDI-> MAC shall be defined in the spec (proposal? I guess in the 100ns…1000ns range together) -
Considering a 1500byte MTU frame with 10GBps (1bit= 0,1ns) the transmission will take a duration of roughly 1,2µs -
When switching data and assuming no disturbing traffic we have to distinguish a stor’n’forward switch and a cutthrough switch. If assuming a worst case store’n forwatrd
switch you have to wait at least until the whole measage is received at the switch (1,2µs) before processing. Additionally some time for the switching itself. So each switch will add about 2µs to the MTU-frame -
5 switches (7 hops) with 2µs will lead to 10µs delay through the switches. With this calculation a 1500byte MTU needs much less then the required 1ms to be present at the receivers MAC-interface.
I think to really nail down to correct numbers we need to align on what does this requirement mean in detail.
Gruß/Regards, Stefan Buntz Stefan Buntz Mercedes-Benz Cars Development, Daimler AG Group Research & Advanced Engineering Safeguarding Hard & Software
HPC: U059 – Dep.: RD/FEQ Phone: +49 731 505-2089
Mobil: +49 176 30 90 51 44
Fax: +49 711 305 216 45 95
E-Mail:
stefan.buntz@xxxxxxxxxxx Address for visitors: Buildung 10 Room 3.2.022 Wilhelm-Runge-Str. 11 D-89081 Ulm Germany |