Hello P802.3dg,
I would like to share another solution to the long-reach encoding problem [1,2].
[1]
https://www.ieee802.org/3/dg/public/May_2024/Lo_3dg_01a_0724.pdf[2]
https://www.ieee802.org/3/dg/public/May_2024/Lo_3dg_02_0924.pdfCompared to the current solution [1,2], the new solution has the following features:
=) operates over a span of 16 transfer units: treats on 16 MII input cycles, outputs a 65-bit block
=) a single transfer unit can represent a data nibble = choice one-of-16 per nibble
=) a couple of two adjacent transfer units can represent a control symbol = choice one-of-8 per octet
+) constant encoding delay of two nibble periods
+) both singles (of data) and couples (of control) are located arbitrarily, with precision of a single transfer unit
+) singles and couples are independent: no dribble nibbles are required
+) every period on MII corresponds to a transfer unit period in a span, as 1 to 1: no tx compressions/rx decompressions
-) information about control symbols may be shared between two adjacent spans, uses AUX bit to avoid such sharing between FEC frames
?) best fits when used with explicit delimiters: SSD, ESD/STILL_IDLE at "background" of data/dummy nibbles
?) (maybe useful) side effect: extra means for "immediate" signaling with 48 user-defined bits per span ("forced output")
Despite I found this as a hobby, I gave it a formal definition (see in attachment).
Because 17-bit blocks are more redundant, the low-latency problem can be solved just mimicking this solution (see also in attachment).
Thanks,
A. Ivanov
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