[10GBASE-CX4] Comments on initial draft of 10GBASE-CX4 PMD
Howard and all,
First of all, my apologies for jumping in somewhat late on this discussion.
I appreciate all the work that has gone into 10GBASE-CX4 to date, and I
hope my comments will be received as they are intended -- as constructive.
I will list several specific comments below, but my overall not-so-hidden
agenda is to persuade the group not to abandon the XAUI compliance interconnect
concept and to avoid required TX near-end measurements. I offer three
reasons for this:
-
(The practical reason) Near-end TX waveforms have maximum high frequency
content, exciting any and all fixture resonances. Hence near-end
measurements -- especially with restrictive templates -- can be a nightmare
of small excursions outside the template. Yet these high frequency
aberrations are attenuated by the transmission path and affect the far-end
signal quality very little if at all. Far end measurements are much
more benign and to the point.
-
(The theoretical reason) A jitter budget, with jitter increasing
down the transmission path made sense for trapezoidal waveforms,
but not for pre-emphasized TX waveforms. With pre-emphasis, the jitter
can be better at the far end of the path than at the TX output. Specifying
such TX waveforms to guarantee an adequate RX waveform is complex and sensitive
to assumptions.
-
(The time-to-market reason) It appears inevitable that the RX will
require additional equalization compared with XAUI. Hence, keeping
the TX specifications as close as possible to XAUI(at least in format)
would seem to offer the lowest risk, fastest route to market for 10GBASE-CX4.
For what it's worth, a compliance channel approach to TX specs would also
render the issue of minimum TX amplitude irrelevant.
Here are some specific comments on sections of the draft:
-
54.7.3.2 Load For accurate measurements of 3.125
Gb/s signals, especially at the TX, 2.5 GHz is probably not adequate bandwidth.
(At the far end, after 12 or 20 dB of attenuation at these frequencies,
this is much less of an issue.)
-
54.7.3.4 Output Impedance and 54.7.4.5 Input Impedance
I realize these sections are out of XAUI, but I would like to point out
that the values specified (if my math is correct) are equivalent to 1.04
pF of dif'l load capacitance on the TX and 0.424 pF of dif'l load capacitance
on the RX. These would be problematic limits.
-
54.7.3.6 Differential Output Template (I gather there has
already been discussion on this item, but I'll add my two cents.)
This template is unworkably tight. The definition of normalized amplitude
guarantees that the waveform will never exceed +/-1, so template values
outside that range are meaningless. This leaves a mere 7 percent
of peak-peak amplitude -- 3.5% at each extreme -- as a target. With
resonances and +/-5% load tolerances, this won't work. The implied
risetimes are also unrealistic. The slowest risetime of a trapezoidal
signal that would fit within the template would have a risetime of 101.4
ps. Realistic, curved waveforms would need to be even faster.
Of course, all these problems go away with the compliance interconnect
approach.
-
54.7.3.7 Transmitter Jitter The added requirement on
the mean of jitter distributions will probably invalidate a number of existing
jitter measurement approaches. A lot of capital equipment might be
obsoleted with this additional requirement.
-
54.8.2 Cable Assembly Insertion Loss Just some questions here.
I do not understand the relevance of the 1/sqrt(f) term. This is
large at low frequency and smaller at higher frequencies. Also, it
should be stated that "f" in the expression is in units of Hz. Also,
I believe the inequality is in the wrong direction. And, lastly,
the sentence ending "...deviate by more than 10% from equation 54.3." might
need some explaining. 54.3 is, after all, an inequality. Does
this allow +/-10% deviation from the right hand side expression?
Or only -10%?
Again, apologies for the last minute comments.
Regards,
Mike
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Mike Jenkins Phone: 408.433.7901 _____
LSI Logic Corp, ms/AH260 Fax: 408.433.2840 LSI|LOGIC| (R)
1873 Barber Lane mailto:Jenkins@LSIL.com | |
Milpitas, CA 95035 http://www.lsilogic.com |_____|
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