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Thank you for the detailed responses. I understand some of the issues and anticipated measurement techniques regarding the transmitter template better now.
Still, I have serious reservations. I think my concern is illustrated in your presentation where adding 2 inches of FR4 induced a change in the mask. Real silicon might pass on a given package and a given PCB yet fail on a different package and PCB. That is the real world (for us, at least). We could not sell a product if we required an ASIC customer to use only certain pins of certain packages and constrain their PCB layout in such a tight fashion.
I suspect that such variations will cause a lot of product to fail the template test, even though they would perform fine in the application. That is, small reflections or resonances which transgress the TX template could be due to high frequency energy which would be virtually eliminated by attenuation at the receiver where the pre-emphasis actually does its magic. I might provide some comparable hardware measurements to show non-compliance, but don't see how one example proves anything. That is, is it the test which would be flawed or the part under test?
Compliance tests which allow product to pass while failing in the application are certainly a disaster, but tests which fail perfectly good product are also a big problem. I see no clear reason why the template is a necessary condition for a product to perform in the application.
The approach which XAUI used and which I had proposed to CX4 -- a Compliance Interconnect -- avoids these difficulties. But the group has decided to go in a different direction. I guess we'll just have to agree to disagree and see how it comes out. I don't enjoy being a nay-sayer, but I have to call it as I see it -- the same as we all do -- for this process to work.
Regards,
Mike
ps: An afterthought -- maybe you could repeat the simulations
with some random variations built into the package and PCB models to get
an idea of the sensitivity?
"Dreyer, Steve" wrote:
Mike,My answers to your comments below in blue.Steve-----Original Message-----Dan,
From: Mike Jenkins [mailto:jenkins@lsil.com]
Sent: Friday, February 28, 2003 4:56 PM
To: DOVE,DANIEL J (HP-Roseville,ex1)
Cc: 'clarkf@mxim.com'; 'stds-802-3-10GBCX4@ieee.org'
Subject: Re: [10GBASE-CX4] comments on latest CX4 revision
I share Clark's concerns. The only related presentation I found for February (cx4_electrical_specs_02_18_03_Raleigh.pdf) showed simulations, not hardware.
The original template was based on simulations from myself and Howard Baumer, and there was plenty of margin against these simulations. . Zeev Roth from Mysticom then contributed the more detailed simulations for the presenatation. Zeev's simulations were deemed to be close to worst case, so we tentatively decided to keep the template limits that barely encompased Zeev's results. The template can be adjusted further, but the group needs to see sim results to be able to do that, if you have some specific results which show problems, please submit to the group so those can be factored in. As far as pre-emphasis tolerance goes, there is some allowance. In case there is any confusion, a waveform is first normalized in amplitude so that the flat pre-emphasis section is sitting on 50% point. So, the actual pre-emphasis value is that 50% point relative to the peak in the template. The peak amplitude template varies from 0.875 to 1.175. Calculating this out shows that the pre-emphasis can be between 42.5-57.5 percent and meet the template. The group thought this was reasonable from an implementation standpoint. Of course, these numbers can be adjusted if somneone has data/results to indicate a problem.
- These simulations used up all the space in the template, passing only when the pre-emphasis was adjusted a couple percent (which is easy to do in simulations, but tough, slow and expensive in silicon).
The group spent a lot of time debating how much "system" tolerance to build in to the spec. It was decided that 2" of FR4 was a reasonable goal. This doesn't preclude anyone from building an IC that accomodates longer lengths and different materials, as long as the spec is met at TP2 anything can be done.
- The need to change the pre-emphasis was due to modelling 2 inches of PCB. What if it's 3 inches instead? or a different dielectric? or a different package?
Agree. No one had any reflection data to present. It was discussed, and most felt that reflections might require an opening up of the template along the flat pre-emphasis section. But it was decided to leave as is pending sim results showing a problem and solution.
- Assumptions in this simulation included perfect impedance matching and no reflections. I very much doubt that a GigaCN-to-SMA adapter board would meet those assumptions.
The DJ spec of 0.18UI was factored in the template. The RJ=0.17UI part was was kept as a separate spec. See working paper draft 3.1.
- No tolerance is allowed for jitter or amplitude noise.
This was addressed by allowing a lot of room on the top of the template on the short pulse section. The amplitude limits go from 0.875 to 1.175, which everyone thought was adequate to address ringing and refrlections. If someone brings in more data to show a problem, the template can be adjusted accordingly.
- Margin for amplitude noise is 10% max, including ringing & reflections.
Agreed. At last meeting, the group decided to add an additional separate rise and fall time spec of 60-130ps (same as XAUI), this was added to working paper 3.1.Apologies if I've missed a presentation with actual hardware compared to this template. But if we're proceeding without any hardware experience, I am frankly concerned that this approach will be a measurement nigntmare. As far as measurement goes, it is true that doing any measurement degrades the signal being observed, but commonly the effects of the measuring equipment are subtracted from the result to determine what the observedsignal actually is. This is true of XAUI measuremnets today where everyone routinely subtracts the effects of SMA connectors, loss of scope cables, degradation due to FR4, etc.Regards,
- Depending on how you model it, slow risetimes (0.41 UI) either just make it or just miss with everything else perfect.
Mike"DOVE,DANIEL J (HP-Roseville,ex1)" wrote:Hi Clark,I believe a lot of your questions would have been addressed
at our meetings. We have had numerous presentations with
measurements of cable assemblies and devices where the first
thing that is done, is determine the impact of the connectors
and PC board, and other impairments on the measurement.Nobody is claiming this is easy, that is not required. It is
necessary to ensure compliance that we have a transmitter that
meets an objective template, and a channel that meets a set of
objective specs, and a receiver that works when connected to
the two former items. Verification is required, but those of
us who have been working on this have spent a substantial
amount of time doing just that.The reason we spec'ed TP2 at the back side of the mated
interface was specifically so that we could get a physical
point as a reference plane.Regards,
Dan
-----Original Message-----
From: Clark Foley [mailto:clarkf@mxim.com]
Sent: Thursday, February 27, 2003 10:30 AM
To: 'ddprocurve@antelecom.net'; 'stds-802-3-10GBCX4@ieee.org'
Subject: RE: [10GBASE-CX4] comments on latest CX4 revisionDan,
Has such a correction for impairments been demonstrated at 3.125Gb/s?
Clark
On Wednesday, February 26, 2003 10:11 PM, ddprocurve@antelecom.net
[SMTP:ddprocurve@antelecom.net] wrote:
>
> Hi Clark,
>
> We discussed this and the conclusion was that there will be some
impairment
> caused by the fixturing (loss, etc) but that must be calibrated out by the
> user. We did not want to get into mandating how much loss, what kind of
> SMAs, etc. Rather, we spec the signal at the interface and rely upon the
> user to be able to make that measurement.
>
> This is consistent with 1000BASE-T and other 802.3 technologies where the
> measurement requires some calibration by the user to compensate for probe
> effects.
>
> Dan
> >
> >
> >54.7.3.6 Differential Output Template and Figure 54-3
> >The interconnect from the MDI to the scope for measuring against this
> >template has not been adequately described. I could not find any
> >information on the plumbing. A tight template like this one must be
> spec'd
> >along with the interconnect hardware.
> >
> >Please consider readily available adapters and cables for this. I
suggest
>
> >that the test interface be comprised of a 1m, 24AWG cable to connect
> >between the MDI and a GigaCN-to-SMA adapter board. If you don't have one> >of these boards yet, you will soon! From the SMA to the scope, we can
use
>
> >short, high quality cable. This is easy and convenient.
> >
> >
> >Regards,
> >Clark Foley
> >Maxim Integrated Products
> >(503) 547-2018
> >
> >-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mike Jenkins Phone: 408.433.7901 _____ LSI Logic Corp, ms/AH260 Fax: 408.433.2840 LSI|LOGIC| (R) 1873 Barber Lane mailto:Jenkins@LSIL.com | | Milpitas, CA 95035 http://www.lsilogic.com |_____| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Mike Jenkins
Phone: 408.433.7901
_____
LSI Logic Corp, ms/AH260 Fax: 408.433.2840
LSI|LOGIC| (R)
1873 Barber Lane
mailto:Jenkins@LSIL.com |
|
Milpitas, CA 95035
http://www.lsilogic.com |_____|
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