Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

[BP] what constitutes the channel



To me it is clear that the "channel" goes all the way from the
Transmitter (the transistors and resistors) to the receiver (the load
and input buffer)  but:  it is also clear to me that the traces on the
chip, the chip pads, the connection from the chip to package and the
IC package are inaccessible to anyone but the IC supplier and as such
it makes no sense to include them in the measured channel.  They are
best considered part of the Transmitter or Receiver.

It is less clear to me that the connection between the package and the
PC board is part of the Rx or Tx but i am willing to go along with
this.

It also clear to me that not all system builders will be willing to
have IC suppliers dictate the design of their PC boards.  If the IC
supplier cannot define the thickness of boards, the number of layers,
the choice of layers used to connect to capacitors, the capacitors
to use, and the distance to the capacitors, it will be impossible for
the IC supplier to guarantee proper operation of the receiver.

I can see two ways out of the problem:

    1.  Have the system designer take responsibility for receiver
        performance by characterizing the path from capacitor to IC
        and requiring extra performance from the IC to cover losses
        in this path.  This solution has two difficulties:

        a.  It requires more performance from the ICs which are likely
            to be hard pressed to work without additional losses.

        b.  It will mean that each system design will require different
            IC designs, negating the advantages of having a standard.

    2.  Put a normative specification on the path from the capacitor to
        the IC.  This could be done in either of two ways.

        a.  Establish specifications on the path from the capacitor
            to IC.  This would involve having another ad-hoc committee
            or another project for the channel ad-hoc, another element
            to be specified, and another element to be added to
            simulation, with uncertainties due to unknown S11 and S22
            phase.

        b.  Lump the path from the capacitor to the IC into the
            "channel."  If there are nasty uncertainties having to do
            with vias to the capacitors etc., i think that it will be
            best to have them out in the open where we can deal with
            them in standards rather than hiding away as implementation
            details.

Note:  when i use the term:  "path from the Capacitor to IC" i intend
        it to include the capacitor, and any vias and pads necessary to
        connect to it but not the connection between the board and the

        IC.

        Low frequency losses due to AC coupling through the capacitors
        will be negligible in the measured range:  with 10nF capacitors
        the loss at 50MHz will be less than 5E-5 dB.

                         charles
--
|--------------------------------------------------------------------|
|       Charles Moore
|       Agilent Technologies
|       ASIC Products Division
|       charles_moore@agilent.com
|       (970) 288-4561
|--------------------------------------------------------------------|