From: Joel
Goergen [mailto:joel@force10networks.com]
Sent: Friday, August
20, 2004 5:08
PM
To: Mellitz, Richard; stds-802-3-blade
Subject: Re: [BP] what
constitutes
the channel
in line ....
Mellitz, Richard wrote:
See
comments below,
…
Rich
Richard,
I read through your presentation and there are a few things to discuss.
I wasn't as clear as I should have been on the clean launch. The data
I
was refereing to clearly shows a single ended launch ... so 8 to 9 ohms
single
ended. I have not looked at the differential response, but would guess
it
should fall within the same 15% passing through a connector thru-hole,
press-fit.
[Mellitz, Richard]
The impedance
issue complicates matters. The launch will create an error. A clean
launch is a launch whose error terms are acceptable to all. I.e the
reference
plane is essentially at pad of unit under test. I think I have shown
that the
results from a good launch and no launch can essentially be equivalent.
I
endorse the concept of a clean launch because is special lab test
feature and
not limited to product restraints. We can spec chips to this.
(joel) I agree
that clean launch can be
specified. The accuracy of it will depend on the geometry and the
reference planes.
I'm pretty much shocked to hear that chip vendors don't have that much
data on
the BGA bad. You will never get a clean launch through the BGA pad
because we just can't carve out the ground or play with the geometry
like you
can on an fxp layout. Lets not forget the necking required to get out
of
the package.
[Mellitz, Richard]
But in the test
board I can use laser drilled vias and Rogers.
On a product we give out guideline for chips. However our legal spec is
to the
pins (or bpg pad) of the device. Many of our designs don’t neck
down to get out of the package. Most lines on server blades can be at
most 6
mils wide. Figure it out 10-14 layer and 62 mils. Oh, the SI effects
of
carving out grounds is over rated. I more of power delivery issue than
SI.
(joel) We are
specifying 'improved fr-4'. We
have already voted on that issue. Please refer to the objectives
document. Rogers
can be used, but is not an fr-4 type material.
(joel) We will disagree on the effects of geometry to reference plane.
I
think the data speaks for itself.[Mellitz, Richard] But if
you are
careful you can mitigate the effects. There are a lot of blade designs
that swizzle
lines through a connector field without any measurable change in from
those that
don’t. But then again there are those where measurable effect can be
detected.
It’s all in the 3-d design.
I can go along with providing a clean launch if all the chip people
agree the
packaging will be 4mm pitch BGA ... yeah ... 4!
[Mellitz, Richard]
Clean launch is a
test anarchism not production feature. So the point is moot. Production
design
is about tradeoffs. We will give guidelines on design but do not
mandate
it if our customers are willing do due diligence on design analysis.
The
spec’s at the pins are necessary for this type of design tradeoff
analysis.
(joel) I
disagree. I see this as a means to
eliminate silicon responsibilty for the BGA pad or to eliminate the
blocking
cap altogether. This is about trade-offs. If the channel has to
include the cap, the SDD21 will drop considerably so NRZ or PAM-4 may
not work
at all. Not sure about any other coding scheme. I don't want to see
coding schems eliminated before they are discussed.
[Mellitz, Richard] I think we are basically
in
agreement. We still need to meet the SDD21 bar even whether the cap is
in there
or not. I believe the improved FR4 was referring to 40 inches. I’ll
agree
you need improved FR to make that happen. Say I want only do 20 inches
on
cardboard at 1/10th the cost. As long as we meet the SDD21
spec I
think we are OK. The signaling decision is partly based on that, the
SDD21 spec.
I’m not suggesting we change that, just the option to put anything
between TP1 and TP4 that meet our needs and the spec.
I think John is right ... signaling should continue to build the
model.
You will find it is not that bad. If the channel has to absorb it, the
schedule is effected, the fr-4 definition is effected, and the SDD21
will drop
considerably. Also, all the work in the channel in terms of cost so
far
will be scrap.
Some type of isolation has been used by IEEE since way back ... either
a
blocking cap or a magnetic. This helps eliminate the common mode
problem
that occurs on large back planes, helps control Differential noise for
EMI, and
makes hot-swap much easier in terms of power supply control ... as you
well know,
most chip vendors now require multiple voltages, as well as power
tracking or
syncronization on the ramp up or down.
[Mellitz, Richard]
I know the
blocking story. There may sides to this and ways to manage CM, EMI, and
power
with out blocking caps. Again all these are design tradeoffs.
(joel) I think
we can agree that neither of us will
agree :):). Lets move on.
I have no issue specifying some type of requirement on the blocking cap
pad or type,
but once you approach the chip package, I can't accept any kind of
control like
that.[Mellitz, Richard]
I don’t
understand what you a getting at. It not cap type
is electrical performance for the cap structure. How you get that is up
to you.
This whole conversation scares me ... it makes me think that all this
time
every chip I have ever used doesn't meet the Sxx11/Sxx22 requirements
that it
should meet because know one understands the pad or can de-embed it for
modeling and test.[Mellitz, Richard]
I did
agree to include the pad even though I think it
should be the Si vendors call. So we are NOT de-embedding the cap.
The real channel goes from TP1 to TP4, with the cap on the rx side. It
always has been this way ... and for good reason. We can not dictate
to
the channel that a cap has to be used should a system designer decide
not to
use it. Placing it in the rx side allows the chip model to either
embarce
it or not. There is nothing stoping the rx side from NOT using a cap.
But place it in between TP1 and TP4 and everyone will have to have it.
The material and channel models become very difficult. We scratch all
our
work and all our design efforts.
[Mellitz, Richard]
Backplane
are different than cables. The old way was
driving form cabling paradigms not dense rack requirements.
I agree
the “real channel”
is between tp1 and tp4. However, I believe that TP1 to Tx and TP4 to
Rx
should be a transparent. I.e. chips measurements with clean launches
into TP1
and TP4 ideally look like the response into the pad. I don’t think
that’s much different from what you are doing with the line cards. Not
we
need a what to determine how good TP1 to Tx and TP4 to Rx is. If we
can
meet that in a real product then TP1 to TP4 must include the cap. This
isn’t much different from the work you already doing. It provides low
cost opportunity which I believe is required.
(joel) Including
the cap in the channel is VERY
different from what we are doing now.
[Mellitz, Richard] I thinks its more like a
twist
than VERY different. The cap belongs to the receiver. This I think we
agree on.
If we can’t meet a TP4 to Rx spec for our board design, we need to put
the cap in the TP1-4 path. The TP1-4 path spec need to be meet. The
problem
this causes is if you want to make Rx eye measurement on a working
system. Which
at 5 GHz I think is meaningless. Want data to illustrate this? Make
the package
lambda anti-resonant and you can close the eye at the pin an be wide
open at
the die. This can be shown with the simplest of simulations.
-joel
Mellitz, Richard
wrote:
I think many Si vendor will take issue with 1 below. So let me see if I
can compromise on 2 to make it more palatable to all.
The track I was on was to define the AC cap and trace to pin of the Rx
as a "clean launch". I think I demonstrated in the presentation that
with close attention to detail and real good "cherry picked" caps, this
can be pretty much done.
The rub is the "real" product channel. I propose that if the AC cap to
Rx is not clean then it is to be included into the channel. I think this
addresses everyone's issues.
Performance: This insures the highest possible performance is supported
by the standard. Superior product design will meet the 40" and more.
Lower cost designs need to make tradeoffs an probably won't reach as
far.
Measurement: This is enabled with the "clean AC launch". Now the issue
we need to address is what is "clean" ... SD11, SD21, etc. Maybe this is
another ad hoc sidebar but I think the measurement experts can plant a
good stake in the ground here.
Silicon Vendors: A clean launch pretty much gets you to the BGA pad as I
demonstrated in the presentation. Since this launch for testing is
relatively transparent, Si vendors should not have serious issues of
including it the Rx.
Board/system designers: Since we now have the "bar" set for performance
(channel spec), board/system designers can trade off connectors,
material, stack-up, etc. We now include the AC cap to Rx as part of the
channel tradeoffs if it's not as "clean" as we would like.
What do y'all think?
Rich Mellitz
Intel Corporation
803-216-2160
-----Original Message-----
From: owner-stds-802-3-blade@listserv.ieee.org
[mailto:owner-stds-802-3-blade@listserv.ieee.org] On Behalf Of Charles
Moore
Sent: Thursday, August 19, 2004 8:04 PM
To: STDS-802-3-BLADE@listserv.ieee.org
Subject: [BP] what constitutes the channel
To me it is clear that the "channel" goes all the way from the
Transmitter (the transistors and resistors) to the receiver (the load
and input buffer) but: it is also clear to me that the traces on the
chip, the chip pads, the connection from the chip to package and the
IC package are inaccessible to anyone but the IC supplier and as such
it makes no sense to include them in the measured channel. They are
best considered part of the Transmitter or Receiver.
It is less clear to me that the connection between the package and the
PC board is part of the Rx or Tx but i am willing to go along with
this.
It also clear to me that not all system builders will be willing to
have IC suppliers dictate the design of their PC boards. If the IC
supplier cannot define the thickness of boards, the number of layers,
the choice of layers used to connect to capacitors, the capacitors
to use, and the distance to the capacitors, it will be impossible for
the IC supplier to guarantee proper operation of the receiver.
I can see two ways out of the problem:
1. Have the system designer take responsibility for receiver
performance by characterizing the path from capacitor to IC
and requiring extra performance from the IC to cover losses
in this path. This solution has two difficulties:
a. It requires more performance from the ICs which are likely
to be hard pressed to work without additional losses.
b. It will mean that each system design will require different
IC designs, negating the advantages of having a standard.
2. Put a normative specification on the path from the capacitor to
the IC. This could be done in either of two ways.
a. Establish specifications on the path from the capacitor
to IC. This would involve having another ad-hoc committee
or another project for the channel ad-hoc, another element
to be specified, and another element to be added to
simulation, with uncertainties due to unknown S11 and S22
phase.
b. Lump the path from the capacitor to the IC into the
"channel." If there are nasty uncertainties having to do
with vias to the capacitors etc., i think that it will be
best to have them out in the open where we can deal with
them in standards rather than hiding away as implementation
details.
Note: when i use the term: "path from the Capacitor to IC" i intend
it to include the capacitor, and any vias and pads necessary to
connect to it but not the connection between the board and the
IC.
Low frequency losses due to AC coupling through the capacitors
will be negligible in the measured range: with 10nF capacitors
the loss at 50MHz will be less than 5E-5 dB.
charles
--
|--------------------------------------------------------------------|
| Charles Moore
| Agilent Technologies
| ASIC Products Division
| charles_moore@agilent.com
| (970) 288-4561
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