Re: [BP] Patterns for the simulation and test
adam,
Test pattern has two disparities (1's-0's or the reverse) of about 300
over 1000 bit times including runs of 46 1's (or 0's). This seems to me
to be stress well beyond 1e-12 probability, at least
3e-14 and more likely close to 1e-15. That is if large disparity it the
key to high stress. So if we use this pattern for the interconnect path
simulation we should take into account that it may represent overkill
for that path and we may want to back off a little from the matching
EITbaseline to get our spec. In a similar vein, if we use PRBS23, that
is unlikely to represent stress beyond 1e-7 for that reason we may want
to increase the spec beyond the matching EIT stress. If someone had time
to do both simulation, we could interpolate.
charles
Healey, Adam B (Adam) wrote:
>
> Collegues,
>
> I recently identified an discrepancy with how IEEE P802.3ap defines
> test patterns for 10GBASE-KR and the previous practice for 10GBASE-R
> port types. I will explain the issue, which will likely correspond to
> the comment from me on the Draft 2.4 recirculation, and also provide a
> suggestion for the simulation exercise that is planned to resolve our
> final technical issues.
>
> Quoting 72.7.1.9 from IEEE P802.3ap/Draft 2.3…
>
> "The data pattern for jitter measurements shall be the pseudo-random
> pattern defined in 49.2.8 with the seed values shown in Table 52-20."
>
> Based on the resolution of comments during the March plenary, the
> interference tolerance test specified in 72.7.2.1 has inherited this
> test pattern.
>
> However, if one was to refer to 52.9.1.1, where Table 52-20 resides,
> one would realize the following:
>
> 1. The seeds representing segments An and Bn are actually intended for
> two different test patterns. Test pattern 1 is two repetitions of the
> 16 896 bit sequence formed by concatenating segments Bn and Bi and
> test pattern 2 is two repetitions of the sequence formed by
> concatenating segments An and Ai.
>
> 2. Quoting 52.9.1.1, "Pattern 1 represents typical scrambled data
> while pattern 2 represents a less typical pattern that could happen by
> chance and is thought to be more demanding of the transmission process
> including the clock recovery subsystem. Both patterns are balanced
> over their length of 33 792 bits."
>
> The testing of 10GBASE-SR/LR/ER port types for stressed receiver
> sensitivity, the closest relative to interference tolerance, requires
> the use of test pattern 2 or a PRBS-31 pattern (named test pattern 3).
> What P802.3ap/Draft 2.4 will, in effect, define is a concatenation of
> half of test pattern 1 and half of test pattern 2. It is not clear
> that there is value in doing this and I am inclined to suggest that we
> follow the model of clause 52 and define the test to use either test
> pattern 2 or 3. I would suggest that this be applied to both transmit
> jitter testing as well as receiver interference tolerance testing.
>
> That said, I will move on to the topic of simulation. I would suggest
> that test pattern 2 be used for simulation, as opposed to PRBS-23 or
> random data as initially suggested. The rationale is that, if one
> wishes to model an interference tolerance test environment, one should
> use the same pathological pattern prescribed for the test.
>
> To support this, I have attached a modestly sized ZIP archive that
> contains ASCII text files with the bit sequences for test patterns 1
> and 2 and a brief summary of the two patterns in the context of
> running disparity, transition density, and baseline wander for
> different coupling capacitor values. I observe that by using a 100 nF
> coupling capacitor (the maximum value suggested in 72.7.2.3), baseline
> wander effects are constrained to +/- 2 mV and may be neglected (but
> perhaps shouldn't be). However, if one, for some reason, prefers to
> use a smaller capacitor value, that judgement would need to be revisited.
>
> I would point out that the patterns are 16 896 bits in length, roughly
> half the size of the PRBS-15 sequence used in our initial studies and
> within the capability of most simulators.
>
> I welcome any discussion or additional input on this topic.
>
> In closing, I would like to thank Bob Noseworthy, Eric Lynskey, and
> company at UNH-IOL for helping me verify that I generated the test
> patterns correctly.
>
> Thank you,
> -Adam
>
>
> <<CLS52TP.ZIP>>
>
--
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| Charles Moore
| Avago Technologies
| ISD
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