Re: [BP] DC block capacitors in 10G NRZ channels
vince,
Our goal is not "to make the SERDES fairly independent of the
coding", it is to make 1000BASE_KX, 10GBASE_KX4, and/or 10GBASE_KR
work. 10GBASE_KR uses 64/66 encoding and will need coupling down to
quite low frequency, 1000BASE_KX and 10GBASE_KX4 use 8B/10B encoding
and can get away with quite a bit higher AC coupling cutoff frequency.
Some IEEE802.3ap compliant transceivers may not support 10GBASE_KR and
would not need as large coupling capacitors and for those cases we
recommend 4.7 nF.
charles
|--------------------------------------------------------------------|
| Charles Moore
| Avago Technologies
| ISD
| charles.moore@avagotech.com
| (970) 288-4561
|--------------------------------------------------------------------|
Cavanna, Vicente Vaca (Sr. ; ProCurve ASICs) wrote:
> Hi Charles, All,
>
> I recognize the problem with 64B/66B coding and AC coupling, but 8B/10B,
> with its guaranteed DC balance over the span of a codeword, does not
> appear to share that problem, and could tolerate a much much smaller
> time constant.
>
> It appears that the goal to make the SERDES fairly independent of the
> coding may be preventing the integration of the AC coupling capacitor
> and thus forfeiting the many benefits of such integration. That is
> unfortunate for the many applications that are likely to use 8B/10B
> coding and that will be forced to share the same difficulties with
> implementation of DC blocks with channels that use 64B/66B or similar
> codes.
>
>
> Vicente
>
>
> -----Original Message-----
> From: Charles Moore [mailto:charles.moore@avagotech.com]
> Sent: Friday, June 02, 2006 10:07 AM
> To: STDS-802-3-BLADE@listserv.ieee.org
> Subject: Re: [BP] DC block capacitors in 10G NRZ channels
>
> While i recognize that putting the AC coupling capacitor on chip would
> be desirable it is not really that easy.
>
> The 100nF off chip coupling capacitor leads to a coupling time constant
> of 10 us. Such a long time constant is needed to limit baseline wander
> with scrambled data, as independent analysis by Rick Walker, Steve
> Anderson, and me indicate.
>
> Generating such a long time constant is going to be hard in today's deep
> sub-micron processes. One could use, for instance, a 100pF capacitor
> and a 100 kOhm resistor, but size of both components would be a problem,
> parasitics in the capacitor will make meeting return loss specs hard and
> leakage current through the 100 kOhm resistor may casue offset problem.
>
> charles
> |--------------------------------------------------------------------|
> | Charles Moore
> | Avago Technologies
> | ISD
> | charles.moore@avagotech.com
> | (970) 288-4561
> |--------------------------------------------------------------------|
>
>
> Jia Gongxian wrote:
>
>>Hi Vicente,Steve,All,
>>
>>I have same concern about the AC coupling, according to the draft,
>>AC compactors does belong to RX, but doesn't clearly say, whether its
>>in linecard or in IC chip, I do think these will cause problems while
>>we design a system. if in linecard, the pad and vias will surely cause
>
>
>>the impedance discontinuity, different processing in AC coupling area
>>of PCB will have different effect on the channel performance. How well
>
>
>>we will process the AC compactors area ? As a system designer, I don't
>
>
>>know, because the spec of backplane channel doesn't include this
>
> part.
>
>>
>>In order to reduce the risk, I do agree Vicente that it's a better
>>choice that place the AC coupling into the IC package.
>>
>>Regards,
>>
>>Jia Gongxian
>>
>>Huawei Technologies Co.,Ltd.
>>
>> ----- Original Message -----
>> *From:* Steve Anderson <mailto:steve.anderson@XILINX.COM>
>> *To:* STDS-802-3-BLADE@listserv.ieee.org
>> <mailto:STDS-802-3-BLADE@listserv.ieee.org>
>> *Sent:* Wednesday, May 31, 2006 11:02 PM
>> *Subject:* Re: [BP] DC block capacitors in 10G NRZ channels
>>
>>
>>
>> Hi Vicente, all:
>>
>>
>>
>> I share your concern. I don't think that the draft
>> standard correctly deals with
>>
>> the topology that you describe. I commented on this in an earlier
>> draft of the standard.
>>
>> I think we need to say what is meant by AC coupling by providing
>
> one
>
>> or more
>>
>> specifications that place some bounds on it.
>>
>>
>>
>> Regards,
>>
>>
>>
>> Steve A.
>>
>>
>>
>>
>>
>>
>>----------------------------------------------------------------------
>>--
>>
>> *From:* Mellitz, Richard [mailto:richard.mellitz@intel.com]
>> *Sent:* Tuesday, May 30, 2006 8:53 PM
>> *To:* STDS-802-3-BLADE@listserv.ieee.org
>> *Subject:* Re: [BP] DC block capacitors in 10G NRZ channels
>>
>>
>>
>> Hi Vicente,
>>
>>
>>
>> 803.3ap really doesn't say the caps are on the board. The cap is
>> after TP4 and is the domain of the Rx. Yes it's a challenge for
>
> chip
>
>> folks as they will need to tell there customers how to deal with
>> this issue.
>>
>> Regards,
>>
>> Rich Mellitz, Intel
>>
>>
>>
>>
>>
>>
>>
>> -----Original Message-----
>> From: Cavanna, Vicente Vaca (Sr. ; ProCurve ASICs)
>> [mailto:vicente.cavanna@HP.COM]
>> Sent: Tuesday, May 30, 2006 6:45 PM
>> To: STDS-802-3-BLADE@listserv.ieee.org
>> Subject: [BP] DC block capacitors in 10G NRZ channels
>>
>>
>>
>> Hello colleagues,
>>
>>
>>
>> I would like to understand the perspective of the group with
>>regards to
>>
>> external DC block capacitors in 10Gbps channels such as the one
>>being
>>
>> designed by this group. My past experience indicates it will be
>>
>> difficult to find DC block capacitors that are specified for
>>operation
>>
>> at 5GHz and beyond - at least capacitors that are priced
>>reasonably such
>>
>> that their cost is a small proportion of the link cost. In the
>>farily
>>
>> recent past I have had difficulty finding capacitors with low
>>enough
>>
>> ESRs even at 4Gbps operation.
>>
>>
>>
>> Even if such a capacitor is found the transmission line
>>discontinuities
>>
>> (vias, pads etc) associated with such capacitors present a
>>significant
>>
>> degradation that would be nice to eliminate.
>>
>>
>>
>> I will ask a secondary question.
>>
>> Has it been considered to require the DC block capacitor to be
>
> internal?
>
>> Many SERDES vendors have DC blocks integrated within their
>>receivers and
>>
>> located downstream from the internal 50 ohm termination but
>>upstream
>>
>> from their receiver bias network (which has much larger impedance
>>than
>>
>> 50 ohms). Such placement allows the capacitor to be much smaller
>>in
>>
>> value and thus integrateable and still allows the receiver to be
>>biased
>>
>> independently of the transmitter which I believe is the main
>>purpose of
>>
>> the DC block. Another benefit of the internal capacitor is that it
>
>
>>will
>>
>> not have the associated discontinuties that an external capacitor
>>will
>>
>> have.
>>
>>
>>
>> Thanks in anticipation of your reply.
>>
>>
>>
>>
>>
>> Vicente Cavanna
>>
>> HP ProCurve Networking
>>