Ad Hoc Meeting Materials (post August 30th, 2012) |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Draft Annex 83D showing changes |
Ryan Latchman | MACOM |
Draft Annex 83E showing changes |
Ryan Latchman | MACOM |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Supporting data for comment against P802.3bm Draft 3.0 related to adaptive CTLE Rx equalization for CAUI4 C2M |
Allessandro Cavaciuti Gary Nicholl |
Cisco Cisco |
Transmitter equalization feedback and MDIO control (In support of comment #i-9) |
Adee Ran | Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Transmitter equalization feedback and MDIO control (In support of comment #i-9) |
Adee Ran | Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Closed-loop TX equalization tuning for CAUI-4 C2C |
Adee Ran | Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
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CAUI-4 Ad hoc (revised) |
Ryan Latchman | MACOM |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Adaptive vs. Programmable CTLE RX |
Marco Mazzini | Cisco |
CAUI-4 CTLE Comments |
Rich Mellitz Adee Ran |
Intel Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Complementary Transmitter and Receiver Jitter Test Methodology |
Ali Ghiasi Greg LeCheminent |
Ghiasi Quantum LLC Agilent (Keysight) Technologies |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
MDIO access to CAUI-4 C2C |
Adee Ran | Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Differences in Jitter specs CAUI4 chip-chip vs 100GBASE_KR4 Update |
Charles Moore | Avago |
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Minutes |
Ryan Latchman | MACOM |
CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
Differences in Jitter specs CAUI4 chip-chip vs 100GBASE_KR4 |
Charles Moore | Avago |
CAUI-4 chip-to-module recommended CTLE register |
Pete Anslow | Ciena |
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CAUI-4 Chip to Chip Burst Errors |
Mark Gustlin | |
CAUI-4 Ad hoc |
Ryan Latchman | MACOM |
CAUI-4 MTTFPA: “Divide and Conquer”? |
Adee Ran | Intel |
CAUI-4 PHY stack ups |
Jeff Slavick | Avago |
CAUI-4 Ad Hoc Meeting Minutes and Straw Poll Results |
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CAUI-4 MTTFPA monitoring |
Pete Anslow | Ciena |
Thoughts on the 100GbE Proposed PCS changes |
Mark Gustlin David Ofelt Gary Nicholl Cedrik Begin |
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CAUI-4 Ad hoc |
Ryan Latchman | Mindspeed |
CAUI-4 C2C lower latency FEC option |
Jeff Slavic | Avago Technologies |
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CAUI-4 Ad hoc |
Ryan Latchman Pete Anslow |
Mindspeed Ciena |
CAUI-4 Ad hoc |
Ryan Latchman Pete Anslow |
Mindspeed Ciena |
CAUI-4 Sinusoidal Jitter Specification: Additional requirements? |
Vinu Arumugham | Cisco |
Multi-lane BIP - proposed draft ammendment |
Pete Anslow | Ciena |
Proposed Change to PCS for multi-lane error detection |
Adee Ran | Intel |
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CAUI-4 Ad Hoc |
Ryan Latchman Pete Anslow |
Mindspeed Ciena |
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SYSTEM CHANNELS FOR IEEE802.3 COM TESTING |
Shaohua Li | Brocade |
(Zip file - Part 1) |
Shaohua Li | Brocade |
(Zip file - Part 2) |
Shaohua Li | Brocade |
(Zip file - Part 3) |
Shaohua Li | Brocade |
(Zip file - Part 4) |
Shaohua Li | Brocade |
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CAUI-4 Ad hoc |
Ryan Latchman | Mindspeed |
Limiting DFE Affect on Burst Error Probability |
Richard Mellitz Adee Ran |
Intel Intel |
Assessing burst rate and MTTFPA in real systems |
Adee Ran | Intel |
CAUI4_main_mez_19p4dB_18mil_stubs (Zip file) |
Richard Mellitz | Intel |
Topology Description CAUI-4 Main Mezzanine Design and 50 mil via stub (19.38 dB) (associated presentation) |
Richard Mellitz | Intel |
CAUI4_main_mez_BRDS_47mil_and_18mil_stubs (Zip file) |
Richard Mellitz | Intel |
Topology Description CAUI-4 Main Mezzanine Design and Back Drilled (13.4 dB) (associated presentation) |
Richard Mellitz | Intel |
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CAUI-4 Ad hoc |
Ryan Latchman | Mindspeed |
MTTFPA (Mean Time to False Packet Accept) for a DFE Design |
Adee Ran Richard Mellitz |
Intel Intel |
TYPICAL CHANNELS FOR CAUI-4 CHIP-TO-CHIP ROUTING IN SYSTEM |
Shaohua Li | Brocade |
Channels_4_CAUI4 (Zip file) |
Shaohua Li | Brocade |
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CAUI-4 Ad Hoc |
Ryan Latchman | Mindspeed |
CAUI-4 CHIP-TO-CHIP CHANNEL ROUTING IN SYSTEM |
Shaohua Li | Brocade |
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CAUI-4 Ad Hoc |
Ryan Latchman | Mindspeed |
Transmitter Characteristics (83D.3.1) |
Ryan Latchman | Mindspeed |
Receiver Interference Tolerance (83D.3.2.2) |
Ryan Latchman | Mindspeed |
Channel Characteristics (83D.4) |
Ryan Latchman | Mindspeed |
A CAUI-4 Specification Method Supporting 15-20 dB Chip-to-Chip Channels |
Mike Li | Altera |
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CAUI-4 Ad Hoc |
Ryan Latchman | Mindspeed |
Transmitter Characteristics (83D.3.1) |
Ryan Latchman | Mindspeed |
Receiver Interference Tolerance (83D.3.2.2) |
Ryan Latchman | Mindspeed |
Channel Characteristics (83D.4) |
Ryan Latchman | Mindspeed |
Proposal for CUI Package and reference Receiver Considerations |
Richard Mellitz Adee Ran |
Intel Intel |
CAUI-4 C2C Transmitter and Receiver Compliance |
Ali Ghiasi | Broadcom |
caui-4_chip2chip_oneboard_meg6_long_20dB_92_ohm_target_board (Zip file) |
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caui-4_chip2chip_oneboard_meg6_long_20dB_92_ohm_target_board_part2 (Zip file) |
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Topology Description |
Richard Mellitz | Intel |
caui-4_chip2chip_twoboards_meg6a_13p39dB_92_110_ohm_target_board_meg6_part1 (Zip file) |
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caui-4_chip2chip_twoboards_meg6a_13p39dB_92_110_ohm_target_board_meg6_part2 (Zip file) |
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Topology Description |
Richard Mellitz | Intel |
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CAUI-4 Ad Hoc (updated post meeting) |
Ryan Latchman | Mindspeed |
CAUI-4 C2C Transmitter FFE Compliance |
Ali Ghiasi | Broadcom |
Jitter at TP0a |
Charles Moore | Avago |
Reference receiver proposal for CAUI-4 chip to chip |
Adee Ran | Intel |
Minutes |
Ryan Latchman | Mindspeed |
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CAUI-4 Ad-Hoc |
Ryan Latchman Alfredo Moncayo |
Mindspeed Mindspeed |
Minutes |
Ryan Latchman | Mindspeed |
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Minutes |
Ryan Latchman | Mindspeed |
CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
CAUI4 chip to chip by leveraging 100GBASE_KR4 |
Charles Moore Rich Mellitz Brian Misek Adee Ran |
Avago Intel Avago Intel |
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15dB_Meg6_LowSR_one_brd_chip2chip_part2 (Zip file) |
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Topology description |
Richard Mellitz | Intel |
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COM Study for 15-20 dB Channels of CAUI-4 Chip-to-Chip Link |
Mike Li | Altera |
CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
Package Impact Data |
Richard Mellitz | Intel |
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CAUI-4 C2C Simulations and Compliance |
Ali Ghiasi | Broadcom |
CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
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CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
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CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
Validation of VSR Module to Host link |
Brian Misek | Avago Tech |
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CAUI-4 Ad-Hoc |
Ryan Latchman | Mindspeed |
A System’s Perspective:CAUI-4 Chip-to-Chip |
Rick Rabinovich Elizabeth Kochuparambil |
Alcatel-Lucent Cisco |
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CAUI-4 Ad-Hoc (Chip – Chip Baseline) |
Ryan Latchman | Mindspeed |
CAUI-4 Chip to Chip Simulations |
Ali Ghiasi | Broadcom |
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CAUI-4 Ad-Hoc (Chip – Chip Baseline) |
Ryan Latchman | Mindspeed |
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CAUI-4 Ad-Hoc (Chip – Chip Spec Baseline) |
Ryan Latchman | Mindspeed |
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CAUI-4 Chip – Chip Spec Discussion |
Ryan Latchman | Mindspeed |
CAUI-4 Chip to Chip Simulations |
Ali Ghiasi | Broadcom |
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Meeting agenda, status and minutes |
Ryan Latchman | Mindspeed |
Option for CAUI-4 Chip to Chip |
Ali Ghiasi | Broadcom |
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Meeting agenda, status and minutes |
Ryan Latchman | Mindspeed |
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Meeting Agenda, Minutes |
Ryan Latchman | Mindspeed |
CAUI-4 Chip-Module Draft Baseline |
Ryan Latchman | Mindspeed |
CAUI-4 Chip-Chip Spec Discussion |
Ryan Latchman | Mindspeed |
CAUI-4 Chip to Chip and Chip to Module Applications |
Ali Ghiasi | Broadcom |
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Meeting Agenda, Minutes and Path Forward |
Ryan Latchman | Mindspeed |
CAUI-4 Chip-Chip Spec Discussion |
Ryan Latchman | Mindspeed |
CAUI-4 Chip-Module Draft Baseline |
Ryan Latchman | Mindspeed |
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CAUI-4 Consensus Building, Specification Discussion |
Ryan Latchman | Mindspeed |