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The method of introducing Skew in my case involves: Cables , pcb, packages and even silicon analog paths etc. may have their own profiles towards combined profile. i.e., in Rich’s equation
∆ is varying over
and
this is introduced in s-param block in each direction and not per port. at present measurements show lot more skew than what we can afford for 224G , limiting
∆ to channel sub-components can achieve in terms of skew.
For example, Cable vendors may guide us for 224G application what we can use as a limit over all freq range of interest– say 1 ps/m or whatever. -Upen From: Richard Mellitz <000014533bad0b9c-dmarc-request@xxxxxxxxxxxxxxxxx>
FYI: This is what how delay was added to a channel in the COM code.
From: Upen Reddy Kareti (ureddy) <00000d999961d690-dmarc-request@xxxxxxxxxxxxxxxxx>
Hi All, Two requests were made during my presentation today– here are my responses
2> Max tap values for under 40 dB insertion Loss – separate stats for the ones passing COM of 3 dB and the ones not passing of 3 dB.
For a case with post cursors of 8 fixed 3 banks (of 4 taps in each bank ) RX FFE span up to 100 UI and Package class B for both Transmitter and
Receiver: Channels < 40 dB and passing 3dB COM. Channels < 40 dB and failing 3dB COM. Regards Upen To unsubscribe from the STDS-802-3-B400G-ELEC list, click the following link:
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