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[802.3_B400G_LOGIC] Final files posted from last week's P802.3dj Joint Logic/Optics Track ad hoc meeting

Hi everyone,

 

The unapproved minutes have been posted.

 

Also, the updated version of Matt Brown’s contribution has been posted incorporating the discrepancies that were pointed out during his presentation.  Thanks to Matt for taking the time to confirm all the data was correct.

 

See https://www.ieee802.org/3/dj/public/adhoc/optics/0423_OPTX/index.html

 

Reminder abut Friday’s deadline for requests on next week’s ad hoc meeting.

 

Thanks,
Mark

 

From: Mark Nowell (mnowell) <00000b59be7040a9-dmarc-request@xxxxxxxxxxxxxxxxx>
Date: Wednesday, April 12, 2023 at 11:16 AM
To: STDS-802-3-B400G-OPTX@xxxxxxxxxxxxxxxxx <STDS-802-3-B400G-OPTX@xxxxxxxxxxxxxxxxx>
Subject: [802.3_B400G_OPTX] P802.3dj Joint Logic/Optics Track ad hoc meeting agenda and details

Hi everyone,

 

A reminder about tomorrow’s joint logic and optics ad hoc meeting.  Call in info is here: https://www.ieee802.org/3/calendar.html

 

Files are mostly posted here and will be fully posted asap: https://www.ieee802.org/3/dj/public/adhoc/optics/0423_OPTX/index.html

 

The presentation agenda will be:

–      "MAC link latency considerations” presented by Matt Brown, Huawei

–      “RS Codeword Interleaving Analysis for 200 GE and 400 GE”, Xiang He, Huawei

–      “SMF Channel Dispersion Penalty Specification Proposal” presented by Chris Cole, Coherent

–      “Towards an 800G-LR4 IMDD Specification” presented by Roberto Rodes, Coherent

–      “oFEC-based 800GBASE-LR1/ER1 proposal with Synchronous Mapping” presented by Gary Nicholl, Cisco

 

 I want to remind all teleconference meeting participants to review the following documents prior to participation in an IEEE 802.3 meeting teleconference:

  • IEEE SA patent policy
  • IEEE SA Copyright Policy
  • IEEE SA Participation Policy

 

All of these policies may be found at http://ieee802.org/3/policies.html

 

 

Thanks,

 

Mark N

IEEE P802.3dj optics track leader

and  

Mark G

IEEE P802.3dj architecture and logic track leader

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