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[802.3_DIALOG] Call for interest - 400Gbps/lane Signaling

Dear Colleagues,

The following request for agenda time for a call for interest has been received from Kent Lusted. It will be discussed at the IEEE 802 LMSC March 2026 Plenary meeting in Vancouver, BC, Canada. If you have any questions, please get in touch with either Kent Lusted <kent.lusted@xxxxxxxxxxxx> or me directly.
 
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With the rapid adoption of Artificial Intelligence (AI) tools and technology, there is a desire to use Ethernet in high-bandwidth, high-growth AI cluster networks, as well as traditional front-end networks for server and switch attachment. The Ethernet community must quickly respond to support the AI network time-to-market requirements and use cases. A number of technology improvements should be investigated to increase the per-lane signaling rate of electrical and optical Ethernet interconnects for the radix-optimized connectivity essential for communication between the high-performance compute devices and intermediate network switch devices.

This call for interest is to initiate a Study Group to develop a Project Authorization Request (PAR) and Criteria for Standards Development (CSD) for Physical Layer specifications supporting existing Ethernet rates using 400 Gbps-per-lane signaling for electrical interconnects as well as optical interconnects with reaches of up to 500 meters.

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The call for interest will take place during the IEEE 802.3 Opening Plenary on the morning of Monday 9 March 2026. A call for interest consensus building meeting will be scheduled to occur during the week. The vote to determine if a Study Group will be formed will take place at the IEEE 802.3 Closing Plenary on the afternoon of Thursday 12 March 2026.

Best regards,
David Law, Chair, IEEE 802.3 Ethernet Working Group
Phone: +44 1631 563729
Email: dlaw@xxxxxxx

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