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[STDS-802-3-EPOC] PHY Link Ad Hoc Notes



All,

I have attached the slides from today's call.  Here is the a summary of the call.


1)      Editor for PLC

a.       Most of PLC will be in the PCS and handled by Marek (digital and framing)

b.      Saif/Joe will handle the rest of it in the PMA.

2)      Huawei and Broadcom presented a Downstream Command Format proposal (at the end of the slides)

a.       Efficient method to set blocks of configuration registers in the PHY.

b.      Marek has concerns about errors in the PLC and impact to incrementing address.

c.       Do we need to have FEC and CRC in PLC?  Do we need to worry about undetected errors multiplying?

d.      Qualcomm wants to consider no address and a fixed register set for PLC.

3)      Baseline Proposal Review (slides 34-35)

a.       One or more PLCs in the downstream is not clear.

b.      1MHz granularity for setting PLC location

c.       General support for 6MHz min size of EPoC spectrum around PLC.  Question on whether it could be 24MHz?

d.      PLC hunting is a vendor specific algorithm but MDIO controls needs to be define.  Bill K will make presentation.

e.      8 or 16 carriers for PLC are adjacent.

Thanks,
Ed...


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Edward Boyd | Sr Technical Director
Broadcom Corporation | (O) 707-792-9008 | (M) 707-478-1146

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Attachment: EPOC-Link-AdHoc-3APR13.pdf
Description: EPOC-Link-AdHoc-3APR13.pdf