Re: [STDS-802-3-EPOC] Link Ad Hoc Notes
Although I do NOT have (at the current time) specific recommendations for the bit fields in the control register, I would expect that the ability to HALT (or PAUSE) PLC hunt/acquisition and the ability to RESTART PLC hunt/acquisition would be useful.
Regards,
Bill K.
From: Marek Hajduczenia [mailto:marek.hajduczenia@xxxxxx]
Sent: Wednesday, April 17, 2013 6:24 AM
To: Bill Keasler; STDS-802-3-EPOC@xxxxxxxxxxxxxxxxx
Subject: RE: [STDS-802-3-EPOC] Link Ad Hoc Notes
Hi Bill,
Can you provide a few words on the PLC_SRCH_ CNTRL (R/W) and PLC_SRCH_ STATUS (RO) registers, that are grayed out in your presentation? I assume, by their name, that the first one is an enable/disable switch, allowing the CLT to remotely control whether PLC hunt is enabled or not. However, if the PLC hunt is disabled, then how can the CNU locate PLC and start working in the first place. I think PLC hunt should be always on, and what we can optimize is the expected range of frequencies that should be scanned in the process of PLC hunting.
I assume that the status register (PLC_SRCH_ STATUS) reflects the PLC lock status (locked / hunting) and makes perfect sense to me.
Perhaps I am off here, but these registers are listed without any explanation and I was wondering what we plan to do with them ...
Regards
Marek
From: Bill Keasler [mailto:bkeasler@xxxxxxxxxx]
Sent: Tuesday, 16 April, 2013 8:48 PM
To: STDS-802-3-EPOC@xxxxxxxxxxxxxxxxx<mailto:STDS-802-3-EPOC@xxxxxxxxxxxxxxxxx>
Subject: Re: [STDS-802-3-EPOC] Link Ad Hoc Notes
I am forwarding some rough notes on the idea of exploiting three MDIO registers to control the frequencies scanned during PLC acquisition. I am hoping to have a few minutes to discuss during the 17APR PHY Link Ad-Hoc.
Regards,
Bill K.
From: Ed (Edward) Boyd [mailto:ed.boyd@xxxxxxxxxxxx]
Sent: Monday, April 15, 2013 11:50 AM
To: STDS-802-3-EPOC@xxxxxxxxxxxxxxxxx<mailto:STDS-802-3-EPOC@xxxxxxxxxxxxxxxxx>
Subject: [STDS-802-3-EPOC] Link Ad Hoc Notes
All,
Sorry for the delay sending out the notes from last week's meeting. The meeting was focused on the baseline proposal for the next meeting. I have attached the slides with the working baseline. The notes are below. Mark; please post the slides. We would like to see proposals on the FEC/CRC for the PLC, preamble for the PLC, hunting procedure, and TDD PLC cycle.
Thanks,
Ed...
Review baseline proposal and questions
- Nicola will have presentation for TDD PLC frame duration
- PLC cycle for FDD is clear due to alignment with pilot pattern.
- PLC cycle for TDD is not clear and needs presentation. Nicola will present in
future meeting.
- Preamble needs definition. Preamble is a single fixed pattern of lower than
QAM16. Preamble is not covered by FEC and infrequent errors in preamble will
not cause bit errors in frame.
- Differences are minor between Duane/Hesham/Ed and Marek's proposal for
instructions. To be discussed at future call.
- FEC+CRC will be considered to determine error performance of channel.
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Edward Boyd | Sr Technical Director
Broadcom Corporation | (O) 707-792-9008 | (M) 707-478-1146
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