Frank,
Thank you for listing your assumptions;
your email helps to clarify a number of issues around use of equalizers.
EDC has been loosely used to refer to many
types of equalizers, but typically means Equalizers dealing with fiber impairments,
which in the case of 10G Ethernet means LRM EDC. The LRM EDC has been
opportunistically proposed to address a whole slew of problems other then
dispersion on OM1 MMF, on the assumption that because it is an 802.3 standard,
it comes for free. The question of exactly how much cost an LRM EDC adds is
complex, so arguments can be made for a broad range of cost adders. Power is
more straightforward; today a LRM EDC adds a significant power increment to
each 10G lane. It is also overkill for most non-fiber impairments like that due
to propagation over FR-4 traces.
As Jack Jewell
pointed out, use of TX pre-emphasis and RX equalization in the host improves
the margin of an SFP+ SR or LR interface. The equalizer type and training is simpler
then a LRM EDC. This translates to lower power. A multi-lane host design,
either for 4x10G or for 10x10G, may include similar equalization techniques. The
key will be to define the multi-lane 10G electrical I/O specification so that
similar equalization techniques optimized for the interface can be employed,
resulting in modest additional power. As pointed out before, because the HSSG MMF
objectives only identify OM3, an LRM EDC is unnecessary.
A host equalizer can compensate for
improperly designed TOSA or ROSA flex circuits, bond wires, ICs, or other
elements. Alternately, these can be properly designed to give the required
overall response. Which then leaves host equalization, if included, to deal
with electrical interconnect between the host IC and Transceiver.
Chris
From: Frank Chang
[mailto:ychang@VITESSE.COM]
Sent: Monday, July 02, 2007 3:57
PM
To:
STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [HSSG] The List
I feel EDC in general term could mean alot
of things to alot of people, and its power consumption
could range from 0 (passive EQ) to over 5-6W and it could be
implemented on the Rx side or Tx side. Not sure what kind
of EDC you meant, which simply did nothing but degrade your
HPC apps.
As to the xtalk, what I meant was the
electrical ones into the EDC input because of multi-10G PMD
lanes which may originate from electrical or optical sources.
The extra EDC margin of 2-3dB I
talked about comes from the efficient bandwidth equalization/optimization
mainly to the RX frond-end in front of the decision circuit as you
can see from a couple of ofc papers we posted. Typically because
of TOSA or ROSA flex circuits, bonding wires, PCB trace etc
associated with large area 10G MMF detectors, the resultant RX frond-end bandwidth
could be as low as 3-4GHz away from the ideal BW of 7-8GHz, such bw
reduction degrades the RX sensitivity dramatically.
From the calculated curve of varying
the Rx frond end BW on the Q-function, the Q-factor roll of
quickly after 6GHz to 3GHz without EDC. When EDC is used to optimized
the bandwidth, the Q-curve could be very flat down to
2.5GHz. We also test some commercial ROSAs, I see sometimes this
margin could be well over 2-3dB.
-----Original Message-----
From: Petar Pepeljugoski
[mailto:petarp@US.IBM.COM]
Sent: Monday, July 02, 2007 11:13
AM
To:
STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [HSSG] The List
Chris,
I
agree with your assessment. If nothing else, the EDC would add to the power
consumption of the module, making things worse for some applications, like HPC.
Frank,
is the crosstalk you are talking about of electrical or optical nature, and
where does it occur?
Thanks,
Peter
Petar Pepeljugoski
IBM Research
P.O.Box 218
(mail)
1101 Kitchawan Road,
Rte. 134 (shipping)
Yorktown Heights, NY 10598
e-mail: petarp@us.ibm.com
phone: (914)-945-3761
fax: (914)-945-4134
|
Chris Cole <chris.cole@FINISAR.COM>
07/02/2007 02:00 PM
|
Please
respond to
Chris Cole
<chris.cole@FINISAR.COM>
|
|
|
To
|
STDS-802-3-HSSG@listserv.ieee.org
|
|
cc
|
|
|
Subject
|
Re: [HSSG] The List
|
|
Frank,
I would be very interested to see your
calculations showing how one gets 2-3dB of extra margin through the use of an
EDC for 10G NRZ optical signal sent over 100m of OM3 MMF (typical BW at 850nm
of 2000MHz/km.)
With respect to EDC for use with
"low-cost" optics, I characterized that as speculative, not enabling.
Chris
-----Original Message-----
From: Frank Chang [mailto:ychang@vitesse.com]
Sent: Monday, July 02, 2007 10:52 AM
To: Chris Cole;
STDS-802-3-HSSG@listserv.ieee.org
Subject: RE: [HSSG] The List
Chris;
I personally agree EDC maynot help reduce or
mitigate cross-talk, instead will provide extra (2-3dB) margin/yield due to
e.g. band limiting effects or dispersion effects if any, existing in OE and EO
conversions or the fiber medium. While this extra margin can be used to
compensate for any penalty induced by xtalk. Like you said, also this could
enable the use of low-cost optics.
Frank
-----Original Message-----
From: Chris Cole
[mailto:chris.cole@finisar.com]
Sent: Thursday, June 28, 2007 6:10 PM
To: STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [HSSG] The List
Ali,
It is not clear what problems are solved by your proposal
to define the 40G and 100G MMF optical specifications around linear interfaces
and host EDC.
Fist, SFP+ 10GE-SR optics are a solved problem
today, and the SFP+ 10GE-SR specification, while not optimum, is complete and
manufacturable. The original 300m meter 802.3 10GE-SR specification has a
number of issues which affect yield and therefore delayed the availability of
low cost 10GE. However, as has been seen from numerous emails on this
reflector, multiple manufacturers have resolved these issues.
On the other hand, the SFP+ 10GE-LRM linear
specification still has a number of difficult issues to resolve. So you are
proposing to consider as a starting point a spec which is still under
discussion and therefore not done, instead of a specification which is complete
and verified to work.
The reason for going to a lower distance for 40G
and 100G is to provide additional margin/yield. Further, 300m multi-ribbon
applications are highly unlikely, so it makes little sense to have the 40G or
100G specifications driven by an insignificant fraction of the applications. We
may re-visit whether 100m is the right distance (150m has been mentioned as an
alternative,) but 300m would be of little value as was commented on by
multiple-end users during the HSSG discussion of the MMF objective.
Second, I am at loss as to how an EDC solves the
additional penalty issue of cross-talk in a multi-lane application. Cross-talk
problems are solved through echo-cancellers, not EDCs. So if we wanted to
reduce cross-talk effects through signal processing techniques, a solution
resembling 1000BASE-T or 10GBASE-T would be required. 10GBASE-T power numbers
in the many watts have been reported on this reflector. For 40G, we would
expect linear scaling in power, and quadratic scaling for full-cross ten-lane
echo-cancellation. We will be well served to view this as a solution of last
resort, not as a starting point.
Third, I do not see the motivation to have an EDC
for an objective which explicitly states OM3 as the fiber. OM3 does not have
dispersion problems over a distance of 100m or 150m. LRM EDC was developed for
legacy OM1 fiber, already deployed within buildings, for example between
floors. I have heard no application identified in any HSSG presentation for 40G
or 100G which would use ribbon-fiber that had dispersion problems like OM1. So
we would burden 40G or 100G hosts with an EDC per channel, so that we can use
optics that do not meet SR specs on the speculatively assumption that they are
lower cost.
Fourth, cross-talk for connectors and PCB traces
has been simulated and quantified (see for example page 12 of
cole_01_1106.pdf.) There is no indication that the cross-talk magnitude is
anywhere near requiring the drastic measures of an EDC/Echo Canceller. A
careful re-allocation of the SFI (SFP+ interface) jitter budget between the
host and optics will permit tolerance of these levels of cross-talk.
Missing is the measurement data for cross-talk in
multi-lane 10G I/O CMOS ASICs. Until we have solid data for this, we will not
be able to complete the specification of MMF PMDs that do not require CDRs.
I would encourage all IC vendors participating in
the HSSG, who have developed silicon that implements 10G I/O, to bring in
multi-lane 10G I/O cross-talk data so that we can base the 40G and 100G
specifications on measurement results.
Chris
----------------------------------------------------------------------------
"Ali Ghiasi"
<aghiasi@broadcom.com>
06/27/2007 12:33 PM
To: "Jack Jewell"
<Jack.Jewell@PICOLIGHT.COM>, "Paul Kolesar"
<pkolesar@systimax.com>
cc: STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [HSSG] The List
Jack and Paul
The question is not whether SFP+ can achieve 300 m
SR reach similar to XFP, but how do we get to 10G SFP+
at 2.5x the cost of 1G classic SFP for DCE (Data
Center Ethernet) with max reach of 100 m.
If we can get to 10G SFP+ at 2.5x the cost of 1G
at 300 m then the 10G PAR objective is complete, but how long
do we wait the need is know. But I do know
the combination of lower cost optics with EDC can deliver
the 2.5x cost objective for DCE applications near
term. To get to these cost the transmitter very likely
will not be fully SR compliant and in that case it
does not matter if the reach is 100 or 300 m.
The current assumption in the HSSG is that you can
achieve SFP+ limiting performance with 4 or 10 channels without the
use of CDR in the module, with more crosstalk,
less optimum layout, SerDes having more jitter and less tolerance compare
to small port count PHYs, optics ??? You
will get small benefit from reducing fiber reach to 100m but not enough to
close the
link budget. As Dan mentioned EDC is
becoming a standard feature on PHYs and we definitely need to leverage it for
40G/100G.
Use of linear interface is an approach that can
close the link budget without the use of CDR in the module, relax the optics
specifications, and the same interface can support
passive copper Twin-ax up to 10m.
Ali