[HSSG] Resend: [HSSG] The List
Dan,
I am trying to learn a little more about this, and I
find your statement in one of your
notes a bit
surprising. You state:
"Regarding 100G performance vs
cost, the argument supporting 100G is not performance/cost
because in the core/WAN, the ability to aggregate multiple 10G channels into a
single channel is paramount and cost is not. If you have 40Km of fiber in the
ground, digging a new trench and running 9 more fibers is not a likely
scenario and you can accommodate a reasonably high cost for that
performance level."
I do not see how
aggregating multiple 10G channels into a single
logical channel
is relevant to
supporting multiple 10G physical channels in a more
compact
format, either through
DWDM, higher bandwidth channels, or ribbon fibers. In
most
present cases, the first
thing the programmers do to a single logical channel
is
cut it apart into
multiple virtual channels for traffic management
purposes.
I would expect that
trend to continue on a high bandwidth backbone.
Instead,
your scenario argues for
higher single serial performance in a single fiber as
well
as DWDM into the same
fiber. In no case does there appear to be a
compelling
argument for creating a
single logical image (or single MAC) for this scenario,
but
rather this argues for a study of
interesting physical layer options combining
multiple 10, 20, or 40 Gb/s single-lane serial
ports, each providing a complete
single logical
channel.
The place where a single
logical image IS important is in transferring
information
to/from an
end-point. And it is precisely that environment that is extremely cost
sensitive.
It requires high degrees
of integration, which argues for something on the order
of
25 to 40 Gb/s to allow a
single serial path (or at worst, a very undesirable
narrow
parallel-serial path) to
be supported from the sourcing NIC chips. And of
course,
such a higher bandwidth
single serial path would also be convenient for packing
into
a single fiber using
DWDM as a component of a core path.
Could you provide some
pointers to HSSG work that demonstrates the necessity
that the 100G core path
be a single logical channel (a single MAC)?
Sincerely,
Robert
Snively