Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: [802.3BA] Why 40GE and not 50GE?

Title: Why 40GE and not 50GE?
Bob/Michael;
 
Another extra point: I'd like to point out 50G in terms of 2x50G was in the discussion as an intermediate upgrade step from 4x25G to serial 100G implementation. I can foresee that this 2x50G system will leverage most chipset/optics developed for 40-43G, (especially for 40G line sides) because of the closest rates. 
 
Regards Frank
-----Original Message-----
From: Grow, Bob [mailto:bob.grow@intel.com]
Sent: Monday, February 18, 2008 9:20 AM
To: STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [802.3BA] Why 40GE and not 50GE?

Michael:
 
I believe the original 40 Gb/s rate was primarily based on the anticipated lower cost of using 4 X existing 10 GbE PHY technology.  Four lanes has significant history in our data paths (e.g., 1000BASE-T, 10GBASE-X4 PMDs, XAUI, etc.)  When P802.3ap was in development, it was generally expected that backplanes could and would be built with 4 10GBASE-KR channels going to a slot, allowing a future upgrade to 40 Gb/s through a single MAC.  Similarly, in the HSSG many advocates used assumed that other 10GBASE-R technologies could be used in a four lane configuration to provide a higher speed connection for servers at lower cost than 100 Gb/s.  OTN compatibility at 40 Gb/s was not an original driving force in the choice of speeds for most advocates.  Just as 10 GbE is 10.0000 Gb/s, so also did the original advocates for 40 Gb/s mean 40.0000 Gb/s.
 
--Bob
From: Frankel, Michael [mailto:MFrankel@CIENA.COM]
Sent: Monday, February 18, 2008 7:11 AM
To: STDS-802-3-HSSG@LISTSERV.IEEE.ORG
Subject: [802.3BA] Why 40GE and not 50GE?


I appologize ahead of time if this question has been addressed.  I looked over past HSSG material, and cannot find any info on how specific 40GE rate came about (as opposed to 50 GE).  40G simply appears as a "fact" in all the presentations.

Is 40G a default selection because of its ties to OC768 and OTU3?

The only item I found is Slide 5 of following presentation mentions PCIe x16 Gen2 as 50 Gbps of bandwidth.
http://www.ieee802.org/3/hssg/public/may07/pepeljugoski_01_0507.pdf


Michael.