Re: [8023-POEP] PoEP
Yair-
The phenomena in "the data transformers are experience voltage
transient due to current imbalance is well known in the
industry"...
... is true for the amount of energy that the PHY chips have to withstand
due to:
- - current associated with the data drivers
- - energy (charge) storage from static build-up in cables
What I don't think has been thoroughly considered by all PHY vendors
is how well their protection works in the face of the significantly
higher energy associated with a PoE or PoE+ disconnect
I believe that the amount of energy they protect against is directly
proportional to the amount of silicon area that they devote to
protection. Therefore the resource is not free. I need input from someone
who is more expert in PHY Si interface design than I am on this to weigh
in here.
Geoff
At 03:22 AM 10/14/2005 , Yair Darshan wrote:
XMLNS:O XMLNS:ST1 XMLNS:U1>
Hi all,
The phenomena in which during asymmetrical connection or disconnection
(Asymmetrical=not all pins are attached at the same time) of a connector
the data transformers are experience voltage transient due to current
imbalance is well known in the industry and taken care off by protection
at the PHY level that clamps the voltage to a low value that prevents
damage.
Yair
From:
owner-stds-802-3-poep@xxxxxxxx
[mailto:owner-stds-802-3-poep@xxxxxxxx]
On Behalf Of Steve Robbins
Sent: Tuesday, October 11, 2005 6:56 PM
To: STDS-802-3-POEP@xxxxxxxxxxxxxxxxx
Subject: Re: [8023-POEP] PoEP
Guys,
This morning I realized
that what I wrote yesterday was incorrect. It's been a long time
since I performed the failure analysis, and I remembered it wrong.
I went back and reviewed the report I wrote. (Sorry I can't post
it. It's an internal Ixia document.)
Anyway, for the record
the big glitches occur when the cable is connected, not
disconnected. (There are also glitches on disconnect, but they are
much smaller.) Here is why the glitches are so big on connector
insertion:
1. Table 33-2 item
1 states that the open-circuit detection voltage can be as high as
30V
2. Table 33-5 item 18 states that the PSE output capacitance during
detection can be up to 520nF.
3. Table 33-2 item 10 states that the PD input capacitance (Csig)
can be up to 150nF
When the RJ-45 connector starts to make contact (not all pins, but some)
there is a inrush current pulse from the PSE output capacitance to the PD
input capacitance. The peak current is limited only by the
resistance and inductance in the loop, which are small, especially for
short cables. This peak can be up to several amps for a few
nanoseconds. Since not all RJ-45 pins are connected when the inrush
occurs, the transformer currents are imbalanced resulting in a large
differential voltage transient (tens of volts) on the PHY side.
The energy stored in the PSE (neglecting cable capacitance) can be up to
234uJ. This energy is low enough such that the ESD protection
diodes in most PHY chips can easily absorb it. But if the PHY has
no protection diodes, the voltage glitches will easily be high enough to
punch through the MOS gate insualation, destroying the chip.
There is also current
imbalance then the cable is disconnected, but the current is only as high
as the load current just prior to the disconnect.
Steve
- -----Original Message-----
- From: owner-stds-802-3-poep@xxxxxxxx
[mailto:owner-stds-802-3-poep@xxxxxxxx]On
Behalf Of Raul Lozano
- Sent: Monday, October 10, 2005 9:23 PM
- To: STDS-802-3-POEP@xxxxxxxxxxxxxxxxx
- Subject: Re: [8023-POEP] PoEP
FYI-
It's Cable Discharge Event (CDE). Several documents explaining this
phenomenon are at:
http://grouper.ieee.org/groups/802/3/ad_hoc/copperdis/public/index.html
Normally the PHY vendors fix this issues in their chip, if not, then
there are other approaches to mitigate the impact from CDE on the PHY
and/or power controller in the case of a POE port.
Regards,
Raul Lozano
Steve Robbins <srobbins@xxxxxxxxxxx> wrote:
Jo and Mike,
In regard to the transient that happens on disconnect, I have
experience with that.
Jo is correct; not all pins on the RJ45 will disconnect
simultaneously. Therefore, for a short time period the transformers
will be severely imbalanced on the PSE side, resulting in a voltage
transient on the PHY side. I've seen these glitches go as high as
60V for a few nanoseconds. We've actually seen at least one PHY
chip that is instantly destroyed by this. Just one or two
insertion/extraction cycles kills it every time. I killed several
of these chips when I investigated this problem last year.
But the problem only seems to occur with one particular PHY chip from
one particular manufacturer, who confirmed that they didn't have any ESD
clamps on the high-speed signals in that chip. This was one of the
first Gig PHY chips on the market, so I guess some bugs are
understandable. FYI, I also found that I could add small external
diodes that protected this device with minor degradation of the eye
pattern due to parasitic capacitance.
All the other PHY chips we've tested at Ixia have survived 100
insertion/extraction cycles in a "worst case" circuit I built
without any apparent damage. But we haven't done an extensive study
of all the PHY chips that are one the market; we've only tested the ones
we use in our products.
Obviously, with the higher current levels proposed for PoE Plus,
there will be significantly more energy in these glitches, but normal ESD
protection diodes should still be able to handle them easily.
Perhaps there should be a new annex added to the standard that explains
this phenomenon, just to be safe.
Steve Robbins
-----Original Message-----
From: owner-stds-802-3-poep@xxxxxxxx
[mailto:owner-stds-802-3-poep@xxxxxxxx]On
Behalf Of Derek Koonce
Sent: Tuesday, October 04, 2005 9:25 AM
To: STDS-802-3-POEP@xxxxxxxxxxxxxxxxx
Subject: Re: [8023-POEP] PoEP
You are correct in the current Mike. I agree the cabling experts
should answer this. However, if they have a lower number I would like to
understand why versus the MIL and NASA specs. It would bee a good
understanding for all of us designers to know what is the true standard
for future cabling needs.
- Derek Koonce
McCormack, Michael wrote:
Jo:
First, let me thank you for your work on these items.
As I recall, the discussion that resulted in 420 mA centered on the
group's understanding of the cable derating requirements. If my
recollection is correct, the cable derating would allow for up to 420 mA
per conductor. This per conductor rating of 420 mA does indeed mean
that the pair would carry 840 mA.
The Study Group felt comfortable defining the characteristics of our
devices but felt we should leave issues that are a result of cabling
characteristics to the cabling experts. You would need to
incorporate the cable systems attributes that you feel are necessary to
our device model in order to complete the total system model.
I am not a PHY expect nor even PHY competent, I will see that the
issue of momentary disconnect under load is brought to the attention of
those who are PHY knowledgeable.
Cheers
Mike
Michael McCormack
Texas Instruments, Power Interface Products
50 Phillippe Cote St.
Manchester, NH 03101 USA
Voice: +1 603 222 8686
Fax: +1 603 222 8580
Email:
mike_mccormack@xxxxxx
Web Site: http://www.ti.com
From: Jo Walling
[mailto:jo.walling@xxxxxxxxxxxx]
Sent: Tuesday, October 04, 2005 8:56 AM
To: McCormack, Michael
Subject: PoEP
Importance: High
Hi Mike,
I am just back from Edinburgh's ISO/IEC meeting. We discussed
there also your letter. There are some points to clarify:
1.) You mentioned that you would like to transmit 420 mA over EACH
conductor. Your sketch shows, however, transmission over the common
mode circuit of two pairs, i.e. over two parallel condcutors. Then
you mention that the circuit components were laid out for 420 mA.
2.) If 420 mA are on each conductor, then the circuit has to be laid
out for 840 mA over the common mode circuit.
3.) The circuit does not yet reflect the capacitance and inductance
of the cabling. I guess this will have to be added by IEC 48B
(Connector group)
Please clarify these points.
I have another questio! n: The blades on the RJ-45 plugs are
crimped onto the condcutors. As a result they are all not exactly
on the same level.
The leads in the connector have also some inherent
irregularities. That means if the plug is pulled out of the
connector, one of the condcutors of the common mode circuit is opened
first, pulling to all likelihood an arc. However the other
conductor is not yet open. As a result the transformer with the
center tap is only on one side loaded. This will create an
induction in the other side, and may affect your chips. Did you
guys consider this?
In Edinburgh we intended first to get back to the now Task Group with
a statement about the maximum ambient operating conditions, which have to
be substantially reduced. However the chair of SC25 requested that
the component groups in IEC are involved first, prior to working out any
recommendation. ! ; You will hear about it more and more detailed either
from Alan Flatman or Massod Sharif.
Kind regards,
Jo Walling
Dr.-Ing. J.- H.(Jo) Walling
Consultant
,
431 Church
Beaconsfield, QC
H9W 3R9, Canada
( Phone: (514) 695-8220 or (514) 695-6063
3 Fax: (514) 695-8220
* Email : jo.walling@xxxxxxxxxxxx