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Hello, The IEEE 802.3at, PoE plus, task force would appreciate
answers from 100BASE-TX PHY vendors
to the following questions before Wednesday April 16. Later submissions
will still be accepted. 1) When was
baseline wander correction added your shipping 100BASE-TX PHYs? 2) What was the
main reason for this introduction? 3) At what
interface is the correction performed (TX, RX, or both)? Why? 4) What is your
and the industry approximate accumulative port volume of 100BASE-TX before and
after the baseline wander correction was introduced? 5) Please
quantify the benefit baseline wander correction provides in terms of Ethernet
transformer bias current. A 100BASE-TX operation requires a 350 uH
transmit (TX) transformer inductance with 0 to 8 mA bias current present. 6) How often
does a 100 MBPS killer-packet occur for a generic Ethernet network? 7) If a
killer-packet occured for a failed data transmission, how probable is a
killer-packet when the same data is retransmitted? 8) Do you
anticipate efforts in IEEE 802.3az (EEE) or IEEE 802.3ba (HSSG) to result in
changes that will affect baseline wander correction or 100BASE-TX? Please
explain. These answers provided will help determine the current
unbalance requirements for IEEE 802.3at. The latest related presentation for
these efforts is available at: http://grouper.ieee.org/groups/802/3/at/public/mar08/schindler_2_0308.pdf Thanks, Fred Schindler Technical Leader CISCO Systems M/S SJ-19-3 Tel. (408) 525-9859 |