Thread Links | Date Links | ||||
---|---|---|---|---|---|
Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
Ed Walker
Technical Staff
Analog Field
Applications
Texas Instruments Incorporated
7001 Weston Parkway
#100
Cary NC 27513
INTERNET: ed_walker@xxxxxx
WEB SITE: http://www.ti.com
Office = 919-677-7061
Fax = 919-677-7030
Just to be clear, we are almost
certainly not putting a battery voltage directly on the
RJ-45.
At the very least each
ethernet UTP port to frame ground needs 2250 VDC of isolation, this is an
existing spec.
When the working
group talks about 48 VDC, we are talking about what the PSE (power sourcing
equipment)
is putting out on
the RJ-45, and it will need to be at least somewhat regulated.
We are now discussing what the voltage range
needs to be.
If someone wants to regulate a 48V
battery voltage to obtain the PSE output voltage, then fine.
If someone wants to regulate a 120V/240V, or
208, 3 phase line voltage to obtain the PSE output voltage, then that's also
fine.
The working group will not be involved
in that decision; that it outside the scope of IEEE802.3af.
IEEE802.3af will only spec the output V, I
of the PSE, not the input power.
Also, the Liaison report was talking
about restrictions beyond SELV.
Some (many?) of us would desire the absolute maximum voltage to be above
48 VDC, like maybe 52 to 56 VDC,
otherwise we will have to limit the available power.
- Rick
-----Original Message-----
From: Tullius, Nick [CRK:0M90-I:EXCH]
Sent: Wednesday, July
19, 2000 6:25 AM
To: Brooks,
Rick [SC5:321:EXCH]
Cc: stds-802-3-pwrviamdi@xxxxxxxx
Subject: RE: power delivery question from Liaison report
Team,
just a reminder that 48 Vdc is a NOMINAL voltage (number of battery cells x 2) and has little to do with the limits of the operating range. The actual float voltage of the battery is 52.08 V (2.17 V/cell x 24 cells) for flooded batteries, and typically 54.00 V (2.27 V/cell x 24 cells). This is obviously the highest voltage ever appearing at the power-to-telecom equipment interface.
These voltages are all within the maximum SELV value of 60 Vdc (see IEC 60950).
For an example of the parameters needed to define a generic 48 V bus, see ANSI T1.315 Voltage Levels for DC-Powered Equipment Used in the Telecommunications Environment.
Best of luck,
Nick
Tullius
Astec Advanced
Power Systems
Tel 613 763-2359
Fax 613 763-7155
ntullius@xxxxxxxxxxxxxxxxxx
-----Original Message-----
From: Brooks, Rick [SC5:321:EXCH]
Sent: Tuesday, July
18, 2000 7:00 PM
To: stds-802-3-pwrviamdi@xxxxxxxx
Subject: power delivery question from Liaison report
I was reading in the Draft Liaison report from
ISO/IEC JTC 1/SC 25/WG 3 to IEEE802.3 on power feeding that was
handed out at the July
Plenary.
IEEE802.3af had question 4: Info on parameter limits (voltage, current, power, source impedance, ...) for world wide standards.
i.e. what are the restriction beyond SELV.
The response back was 48 VDC max, 175 ma max per pin.
My question is:
Is the 48VDC output from the
port really 48VDC max as the response to
the question indicates?
If so, my thoughts are the following:
We would have to spec our power output at the PSE
as 48 VDC + 0%, - 8%, or something like that,
so that it never exceeds 48
VDC continuously.
This will further limit the available load
power;
it would be
less than the load power that was discussed at the last meeting namely 14.6
watts.
So, in that case the PD must be designed to draw
at most 350 ma, as we discussed.
And the power delivered at 100 meter cable would then
be:
Pwr = [44.2 -
(12.5 x 0.35)] 0.35 = 13.9 Watts. (where 44.2 VDC is the lowest output
voltage to still be in spec)
For long cable lengths, the current per pin will be
balanced, and we don't exceed the 175 ma per pin.
For short cable lengths, we probably need an
additional power spec, so that neither RJ-45 pin exceeds 175 ma.
Say that due to connector
imbalance, one pin is 175 ma, and the other is 20% below that, or 140 ma,
which is a total of 315 ma.
Then the power for a short cable would be (at least) 13.9 watts (44.2 * 0.315).
This would say that the PD device should be
designed not to draw more than 350 ma,
and at the same time not to
draw more than 13.9 watts.
That way we never exceed 48 VDC nor 175 ma per pin on a
continuous basis.
This puts the burden on the PD end to meet these
current and power requirements.
The PSE end would have a max voltage of 48 VDC, but it's
current limit would be set slightly higher than 350 ma
by some appropriate
margin.
If, on the other hand, we put the burden at the PSE end, then the available power goes down even more, but that may be OK also.
comments?