RE: insuring the stability of power delivery
Rick, Yair, others,
I've added comments below. I have added ===== signs
between topics to help readability (I hope)
Brian
>-----Original Message-----
>From: Yair Darshan [mailto:YairD@xxxxxxxxxxxxxx]
>Sent: Wednesday, May 30, 2001 8:44 PM
>To: 'Rick Brooks'; stds-802-3-pwrviamdi@xxxxxxxx
>Subject: RE: insuring the stability of power delivery
>
>Rick and all,
>See my comments below.
>Yair.
>
>> -----Original Message-----
>> From: Rick Brooks [SMTP:ribrooks@xxxxxxxxxxxxxxxxxx]
>> Sent: ה, מאי 31, 2001 1:02 AM
>> To: stds-802-3-pwrviamdi@xxxxxxxx
>> Subject: insuring the stability of power delivery
>>
>> Hi,
>> I just wanted to voice one concern that I have regarding
>power ramp up,
>> and continuous power modes.
>> I was reminded of this issue when I was simulating the
>current limits in
>> the PSE and PD and watching
>> oscillations on the cable during startup. Yair's Pspice
>circuit does not
>> have these problems
>> due to the fact that there are Op-amps in the current limit
>feedback loops
>> (i.e. band limited).
> [Yair Darshan] Correct, in a typical design, the bandwidth is
>limited, thus preventing oscillation.
> If you are using behavioral
>models that are
>not limited in bandwidth, you should expect oscillations.
> In my model I have used real
>circuit model which is bandwidth limited, therefore, no oscillations
[Brian Lynch] I think there is more to it than that. True the
behavioral models may have higher bandwidth than "actual models"
(which in Yair's case are actually characterized behavioral models,
not actual circuit models), but that does not guarantee a circuit
will be free of oscillation. Depending on the gain and phase of the
circuit, it may be just of lower frequency.
=================================================================
>> It seems to me that we do not yet have a defined and
>specified behavior
>> that will insure that the DTE power will be
>> delivered in a stable way.
>> How do we guarantee that a PD from vendor "A" will not oscillate when
>> connected to a PSE from vendor "B"?
>> The PD as an electrical load needs to be dominated by a capacitive
>> reactance.
>> I think that we all agree, but this has not yet been specified.
> [Yair Darshan] I agree that we need to specify "something" to
>insure inter-operate, however it is not an easy task since a lot more
>involved here.
> The PD is not just a capacitive
>load, it is
>also a load with negative resistance which is frequency
>depended and has
>poles and zeros at its
> reflected input impedance.
> Your point is equivalent to the
>following question: How a manufacture of standard switching
>power supply
>ensure that his power supply will be stable when it is
>delivering power to a
>load that is also a dc/dc switching converter. There are no
>standards for
>this issue since the number of application and scenarios are
>un limited.
>However, there are some "golden" rules that help to minimize
>those problems.
> 1. Keeping low ratio of L/C . L is the line inductance. C is the
>input capacitor of the load (PD power supply input.) It means
>relatively
>large capacitance at PD power supply input.
> 2. The total impedance's of the source output and the load input
>should be positive (hard to define but possible)
> 3. Add some series loss to the cable (resistor).
[Brian Lynch] I agree with some of these points: 1) The impedance at
each end of the cable should be small with respect to the Z of the
cable. This is relatively easy to do for low frequencies. Care should
be taken to insure that there is sufficient capacitance at high
frequencies (i.e. use some ceramic caps which have low ESR and ESL).
This will take care of any ringing on the cables.
In our work with power systems, we have found that to insure
stability of a system, the closed loop output impedance of the
sourcing supply must be lower than the closed loop input impedance
if the load power supply over the frequency band and voltages
of interest. This concept is also discussed and taught at various
universities. VPI and MIT are two I have direct knowledge of.
To 802.3af, that means the closed loop output impedance
of the PSE must be lower than the closed loop input impedance of the
PD from 1Hz to some TBD frequency over the operating voltage range.
Adding cable to the mix: The closed loop output impedance of the PSE
plus the maximum cable impedance (R and L) must be lower than the
closed loop input impedance of the PD plus the maximum cable impedance
(L and R)=> Since we do not know the cable length to insure system
stability, the closed loop output impedance of the PSE plus the cable
impedance must be less than the PD's closed loop input impedance.
Notice that I have said "closed loop" impedance. This means that the
feedback loops of the PSE power supply and PD DC/DC converter plus the
load of the PD are included in the calculations. Not an easy task for
an open standard.
If we could get plots of the output impedance of a number of PSE supplies,
add in the known maximum cable impedance and some margin, we could get
an idea of the minimum input impedance we could allow for a PD. Then
we could specify both curves as a requirement.
=====================================================================
>
>> During power ramp up, either the PSE or PD current limit will be in
>> effect, so we need to specify the behavior
>> during power ramp up.
> [Yair Darshan] If you have current limit at the PSE,
>you solve most
>of the problem since you have one side with limited bandwidth
>and the most
>important thing is
> that you put dissipative element in series to the cable
>that damps
>the oscillations very rapidly or prevent them from starting.
>(Meets rule 3
>above)
[Brian Lynch] I disagree with the reasoning here. A if inrush current
limiting is in the PSE, then by definition, it goes into a high impedance
state (current limiting turns the PSE from a voltage source into a current
source) during start up. The reason the system doesn't oscillate is
because the capacitor is a steady state load as it charges. This is
independent of whether the current limiting is done with a dissipative
element (as is our case) or done by another means (as is done in most
commercial switching power supplies). If the load had a dynamic element
to it, such as a motor starting, we very well might see oscillations.
The problem I have with PSE inrush current limiting is the fact that the
voltage at the PD input port drops below the 30 volt limit for a period
of time as the bulk capacitor charges. A problem solved by putting
inrush limiting in the PD.
===================================================================
>> At the present time, what behavior is specified to insure
>that the PSE
>> feedback loops,
>> either to regulate the output voltage, or to limit the
>current (protection
>> circuits),
> [Yair Darshan] Limit the PSE output current is the
>most effective
>way.
[Brian Lynch] I don't follow how this answers Rick's question. For system
stability, I think we should specify a maximum PSE output impedance vs.
frequency curve, and a minimum PD input impedance vs. frequency curve.
This is independent of the inrush-current-during-startup discussion because
startup and operation are two different modes, with a different set of
issues.
====================================================================
>> will not oscillate with the longest UTP cable or the PD?
>>
>> It seems that we need to address these issues or we do not
>have a complete
>> standard.
> [Yair Darshan]
> If we specify that the PSE have a current limit (which we did
>already) we have 90% of the solution. In this case the PD will
>need to meet
>standard
> design rules that do not need to be specified. In any
>case we should
>analyze this concept under some typical operational envelope
>that should
>include the following parameters:
> PSE output current limit bandwidth which is
>unconditionally stable.
> PD min. input capacitor
> Cable max. inductance.
>
[Brian Lynch] Just specifying the current loop bandwidth of the PSE is
a partial solution, and specifying a PD capacitance is limiting to future
designs and assumes the PD input impedance is capacitive (which may or
may not be the case 5 years from now for ALL PDs.)
I would prefer to see impedance curves which guarantee stability no matter
what
the cable lengths are..
============================================================================
>> Some ideas:
>> 1) specify the maximum loop bandwidths of the PSE and PD
>loops so that any
>> such system will always
>> behave as a lumped circuit. In other words, spec the loop
>bandwidth so
>> that it is about 6 to 10
>> times smaller than 1/lambda of the maximum length UTP cable.
>> We do not want sudden load changes to cause oscillation or
>ringing, for
>> instance.
>> Slew rate helps, but it is a large signal behavior only.
>>
>> 2) specify a minimum phase margin into a "standard" PD load
>(whatever that
>> is)
>>
>> 3) specify a maximum gain at the UTP bandwidth at the longest cable.
>>
>> 4) both the PSE and PD need to have a specified behavior.
>>
>>
>> Any other ideas or discussion on this topic?
>> How about you power guys???
> [Yair Darshan] See above.
>
> Yair.
[Brian Lynch] Rick, I think you are on the right track. I don't think
we need to specify loop gains or phase margins. If we limit the PSE's
output impedance and the PD's input impedance over the voltage range
and frequencies of interest, I think we have normal operation covered.
As a starting point, I'll recommend: 30 to 57 volts and 1Hz to 10Mhz.
Startup is a special case where different curves may apply. If we hold to
the
PSE's output impedance is to be less than the PD's input impedance, then
that
puts inrush limiting in the PD. My thinking is this: During non-fault
operation
(i.e. short across the port's wires) the output of the PSE should be a
voltage
source. This keeps the output impedance as low as possible without adding
any cost or special circuitry. In the PD, adding inrush current limiting
adds impedance to the input of PD and helps to improve system stability
during startup.
How about comments from others?
Brian
>> thanks,
>> - Rick
>>
>