RE: [10GBASE-T] RE: PAR and 5 critters
Hello, Sreen,
>I have to disagree with your analysis. In HDD read channels, you are trying
>to detect a 2-level signal (binary). Due to partial response channel
>shaping, the slicer initially slices the equalizer output to 11-levels, when
>further get reduced to a 2-level decision by ISI- sequence detector.
I agree.
>In PAM-10 modulation, we are trying to decode between 11 transmitted symbols
>as opposed to 2. The uncoded SNR needed goes up by 6 dB for every doubling
>of transmitted symbols, which means that you need an additional 14 dB of
>detection SNR for decoding PAM-10 signals.
>In addition, HDD read channels do not suffer form 50 dB of channel
>attenuation, or need echo cancellation, both of which further increase the
>requirements of the ADC needed.
I disagree.
If no equalization is located in front of ADC, I can understand
your saying.
First of all, assuming all channel equalization can be done
in analog frontend before ADC, for example equalizing filter in RX
or pre-emphasis in TX, crosstalk cancellers using analog FIR filters
and DFE with DAC, etc.
If we can complete flat frequency response under Nykist frequency
and cancel crosstalks, even pessimistic, ADC only needs to detect
10 level signal + noise, and a couple of bit to earn coding gain.
The coming "Noise" doesn't depend on ADC quantization noise.
Ideally you cap put digital LPF after ADC to get same SNR condition.
More optimistic solution is not to be flat frequency response
before ADC. In the case, 10PAM signal will make ISI and to be
more multi levels. The level number or ADC resolution depends
equalized frequency response or single pulse response before ADC.
This is design matter or detail spec matter.
As I mentioned in my previous mail,
4 generation finer process gives us >10 times higher speed, and
we can get higher accuracy at least using over sample technology.
Other higher accuracy technology can be applied.
We can design higher resolution ADC for 90nm or 65nm process,
if needed for the dedicated design.
I can agree that ENOB is required approximate 10bit level, but it
doesn't mean 10bit resolution ADC is required.
What I want to say is "feasible at analog point of view".
Actual physical design is a balance between ADC complexity and
analog equalization and cancellation complexity.
It should be between full analog equalization + cancellation
and no analog equalization + cancellation.
Sugawara
-------------
From: "Sreen Raghavan" <sreen-raghavan@vativ.com>
To: <sugawara@necelam.com>, <stds-802-3-10gbt@ieee.org>
Subject: RE: [10GBASE-T] RE: PAR and 5 critters
Date: Wed, 30 Jul 2003 10:25:47 -0700
I have to disagree with your analysis. In HDD read channels, you are trying
to detect a 2-level signal (binary). Due to partial response channel
shaping, the slicer initially slices the equalizer output to 11-levels, when
further get reduced to a 2-level decision by ISI- sequence detector.
In PAM-10 modulation, we are trying to decode between 11 transmitted symbols
as opposed to 2. The uncoded SNR needed goes up by 6 dB for every doubling
of transmitted symbols, which means that you need an additional 14 dB of
detection SNR for decoding PAM-10 signals.
In addition, HDD read channels do not suffer form 50 dB of channel
attenuation, or need echo cancellation, both of which further increase the
requirements of the ADC needed.
Sreen Raghavan
Vativ Technologies
>-----Original Message-----
>From: owner-stds-802-3-10gbt@majordomo.ieee.org
>[mailto:owner-stds-802-3-10gbt@majordomo.ieee.org] On Behalf Of
>sugawara@necelam.com
>Sent: Tuesday, July 29, 2003 7:43 PM
>To: stds-802-3-10gbt@ieee.org
>Subject: [10GBASE-T] RE: PAR and 5 critters
>
>
>Hello, everyone,
>
>I believe it is not easy but doable job to realize 10G base-T analog
>frontend based on my previous experiences.
>
>In ISSCC '97,'99, and '01, we demonstrated this kind of technology
>for HDD readchannel devices. The '01 paper described 2.5years ago;
> 700MHz, 11 level detection (equivalent to 11PAM) by ADC with
> sample & hold,
> compensating channel responses by combined 7th order analog filter
> and 8tap digital filter,
> connected to a Viter Bi detection,
> using 0.18um BiCMOS.
>This is an old technology.
>
>Now 90nm process is available and 65nm and beyond will be popular
>in 2006 when 10G Base-T will be standardized.
>In the time, even CMOS can be designed at much higher speed
>operation.
>
>We can use over sampling technology to earn more effective bits, at
>least. We can use analog cancellation mentioned by Dr. Spencer in
>July plenary, as well as frequency response compensation above.
>These are some design options.
>
>At this time, do we need more investigation for analog frontend ?
>
>
>
>Mitsutoshi SUGAWARA
>NEC Electronics America Inc.
>Director Analog Engineering
>
>
>>Sreen,
>>
>>Over the course of last four IEEE 10GBASE-T SG meetings plus
>>the CFI (Nov. 2002) and through several presentations I have
>>highlighted the difficulty of realizing a stand alone CMOS ADC
>>with ~1GS/s and ENOB=11 bits. I have also pointed out the
>>problem of jitter-limited ENOB that is a result of integrating
>>four such ADCs along with large number of digital gates on the
>>same chip.
>>
>>I have also offered some alternative solutions that involve
>>implementing part of the signal processing in analog. The
>>following three bullets are borrowed from Prof. Richard Spencer's
>>July presentation:
>>
>>*A mostly digital (DSP) solution will severely tax the sate-of-
>> the-art ADC capabilities
>>
>>*The AFE could include significant equalization to reduce burden
>> on the ADC and back end DSP
>>
>>*The AFE might also include some echo cancellation and/or NEXT
>> cancellation
>>
>>
>>http://www.ieee802.org/3/10GBT/public/jul03/spencer_1_0703.pdf
>>
>>
>>I agree with you that traditional AFE + DSP approach, in this case,
>>runs into trouble however, alternative approaches do exist. Some
>>of these approaches have been successfully applied to high data-rate
>>read channels.
>>
>>Regards,
>>
>>Joseph N. Babanezhad
>>Plato Labs.
>>
>>
>>-----Original Message-----
>>From: "Sreen Raghavan" <sreen-raghavan@vativ.com>
>>To: "'Kardontchik, Jaime'" <jaime@integration.com>, <stds-802-3-
>>10gbt@ieee.org>
>>Date: Tue, 29 Jul 2003 15:35:04 -0700
>>Subject: RE: [10GBASE-T] PAR and 5 critters
>>
>>>
>>>
>>> I understand there is a huge difference between implementing a 7-bit
>>> precision ADC and an 11-bit precision ADC.
>>>
>>> Sreen Raghavan
>>>
>>> -----Original Message-----
>>> From: owner-stds-802-3-10gbt@majordomo.ieee.org
>>> [mailto:owner-stds-802-3-10gbt@majordomo.ieee.org] On Behalf Of
>>> Kardontchik,
>>> Jaime
>>> Sent: Tuesday, July 29, 2003 2:53 PM
>>> To: stds-802-3-10gbt@ieee.org
>>> Subject: RE: [10GBASE-T] PAR and 5 critters
>>>
>>>
>>> Yeah, the analog target specs look reasonable ...
>>>
>>> For comparison, in my previous life (company) I did some
>>> system simulations (and actual design) and came to the
>>> conclusion that one could run 10 Gbps over cat-7 STP to
>>> a distance of about 25 meters with a 7-bit effective ADC
>>> at 625 Mbaud (PAM-5 modulation). At least, the 7-bit
>>> effective ADC was achievable ...
>>>
>>> Jaime E. Kardontchik, PhD
>>> Integration
>>> Mountain View, CA 94041
>>>
>>> -----Original Message-----
>>> From: Sreen Raghavan [mailto:sreen-raghavan@vativ.com]
>>> Sent: Tuesday, July 29, 2003 1:58 PM
>>> To: 'DOVE,DANIEL J (HP-Roseville,ex1)'; sreen@vativ.com; 'Alan
>>> Flatman';
>>> Kardontchik, Jaime
>>> Cc: '[unknown]'; 'Sterling Vaden'
>>> Subject: RE: [10GBASE-T] PAR and 5 critters
>>>
>>>
>>> Dan:
>>>
>>> We are really referring to the theory (Shannon Capacity) when we say
>>> 10Gbps
>>> cannot be achieved over CAT-5e or CAT-6 cabling. Theory shows that
>>> 10Gbps
>>> can be achieved over CAT-7 cabling. Practical issues to accomplish
>>> 10Gbps
>>> over CAT-7 cabling include (assuming PAM-10 modulation):
>>>
>>> 1. Building an 11-bit effective ADC at 833 MBaud,
>>> 2. Performing large number (x8 relative to 1000BaseT) of DSP
>>> calculations at
>>> 833MHz,
>>> 3. DDFSE critical path to be implemented in 1.2 ns
>>> 4. Building a linear transmit driver with an 833MGz bandwidth & 40 dB
>>> SNR
>>>
>>> The above list by no means is exhaustive, but shows the implementation
>>> issues that need to be considered.
>>>
>>> Sreen
>>>
>>> -----Original Message-----
>>> From: DOVE,DANIEL J (HP-Roseville,ex1) [mailto:dan.dove@hp.com]
>>> Sent: Tuesday, July 29, 2003 1:09 PM
>>> To: 'sreen@vativ.com'; 'Alan Flatman'; 'Kardontchik, Jaime'
>>> Cc: '[unknown]'; 'Sterling Vaden'
>>> Subject: RE: [10GBASE-T] PAR and 5 critters
>>>
>>> Hi Sreen,
>>>
>>> One thing that occurs to me on this point is the difference between
>>> theory and application. Specifically, how many process actions have to
>>> take place within a baud time to close the loops on the DSP and what
>>> process geometry would be required to make that timing closure?
>>>
>>> I know that with 1000BASE-T, the theory was rock solid long before the
>>> processes to implement it were reliable.
>>>
>>> Dan
>>> HP ProCurve
>>>
>>> > -----Original Message-----
>>> > From: Sreen Raghavan [mailto:sreen-raghavan@vativ.com]
>>> > Sent: Tuesday, July 29, 2003 11:52 AM
>>> > To: 'Alan Flatman'; 'Kardontchik, Jaime'
>>> > Cc: '[unknown]'; 'Sterling Vaden'
>>> > Subject: RE: [10GBASE-T] PAR and 5 critters
>>> >
>>> >
>>> >
>>> > Just to clarify, Vativ, Broadcom & Marvell presented capacity
>>> > calculations
>>> > at the Portsmouth meeting and showed that worst-case CAT-7
>>> > (Class F) cabling
>>> > had sufficient channel capacity to achieve 10Gbps throughput
>>> > at 100 meter
>>> > distance. The reason for "may be possible" statement in the
>>> > conclusions was
>>> > that the 3 PHY vendors felt that more work needed to be done
>>> > on practical
>>> > implementation issues before the conclusion could be altered to a
>>> more
>>> > definitive statement.
>>> >
>>> > In addition, we proved conclusively that there was NOT
>>> > sufficient channel
>>> > capacity on existing CAT-5e (Class D), or CAT-6 (Class E)
>>> > cables to achieve
>>> > 10 Gbps throughput.
>>> >
>>> > Sreen Raghavan
>>> > Vativ Technologies
>>> >
>>> > -----Original Message-----
>>> > From: owner-stds-802-3-10gbt@majordomo.ieee.org
>>> > [mailto:owner-stds-802-3-10gbt@majordomo.ieee.org] On Behalf
>>> > Of Alan Flatman
>>> > Sent: Tuesday, July 29, 2003 9:51 AM
>>> > To: Kardontchik, Jaime
>>> > Cc: [unknown]; Sterling Vaden
>>> > Subject: RE: [10GBASE-T] PAR and 5 critters
>>> >
>>> >
>>> > Message text written by "Kardontchik, Jaime"
>>> > >Was any reason given why it would not run on Class F ? Was it for
>>> > technical reasons or for marketing reasons ?<
>>> >
>>> > The 3-PHY vendor presentation made in Portsmouth (sallaway_1_0503)
>>> > calculated 49.36 Gbit/s capacity using unscaled Cat 7/Class F
>>> > cabling. This
>>> > figure was reduced to 37.71 Gbit/s with worst case limits. Overall, I
>>> > thought that this was a refreshingly realistic presentation and I
>>> > interpreted the summary statement "Capacity calculations with
>>> > measured data
>>> > indicate 10 Gigabit data transmission over 100m Cat 7 may be
>>> possible"
>>> > (slide 16, bullet 3) as overly cautious engineering judgement.
>>> >
>>> > So, what has changed since the May interim? Not the laws of physics!
>>> >
>>> > Best regards,
>>> >
>>> > Alan Flatman
>>> > Principal Consultant
>>> > LAN Technologies
>
>
>
>
Regards,
== Mitsutoshi SUGAWARA == NEC Electronics America Inc.==
Director Analog Engineering, Broadband LSI Technology
Phone:(408)588-5222, Fax:(408)588-5252, M/S SC2304
Email: sugawara@necelam.com, msugawara@ieee.org
===== 菅 原 光 俊 ==== ＮＥＣエレクトロニクスアメリカ==== JA1URI ====
Director Analog Engineering, Broadband LSI Technology
Tel:001-1-408-588-5222(NEC内線8-00-01-941-5222) Fax:-5252(NEC内線-5252)
e-mail: sugawara@necelam.com, msugawara@ieee.org 封書メール記号:SC2304