[8023-10GEPON] Example of why doing FEC after scrambling needs careful analysis
All,
During the Q&A after Frank's presentation, I mentioned that it was not obvious that a FEC's output always has statistical DC balance and sufficient transitions. This is particularly true given the fact that his proposal used a RS(255, 239) code, but only used 231 bytes of the input instead of the full 239.
I thought it would be good to present a simple example which illustrates the problem case. That example is:
If any given bit of the added FEC parity was based only on the bits in the unused pad, it would end up with a fixed output value,
independent of any preset value of that pad. This would then break the DC balance property.
I assume that it is possible to define a FEC algorithm that acheives DC balance and has sufficient transitions, but it should not be accepted without analysis.
Alternatively, FEC algorithms exist that have the capability of unwinding the known, fixed error muliplication caused by operation after a self-synchronous scrambler.
Brian Holden
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Brian Holden PMC-Sierra, Inc.
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