[8023-10GEPON] FEC vectors adhoc
Per Glen's request, here is an outline for the work on FEC test
vectors...
1. The following people have indicated interest in the FEC vectors work:
Fumio Daido - Sumitomo
Frank Effenberger - Huawei
Dongning Feng - Huawei
Ryan Hirth - Teknovus
Seiji Kozaki - Mitsubishi Electric
Additional participation is welcome.
2. Work items
The discussions in Orlando did a lot to clarify the bit order and text
interpretation issues.
I am currently preparing revised vectors that incorporate the TF's
Orlando decisions on bit order and some additional text to disambiguate
the notation and processing for each step as much as possible.
There are basically two work items:
a) Arrive at an agreed-upon set of parity blocks for a
particular set of input blocks
- this may involve some additional discussion to clarify
bit order etc.
b) Resolve any issues of vector presentation:
- ie. mainly the issue of notation for presentation of
input and output 66b blocks, but there may be other issues
3. Schedule
March 30 - Distribution of revised vector text (Jeff)
March 30 - April 3
* Email discussion of algorithm issues
- these should be minimal, since we did a good job of it
in Orlando and afterward
Confirmation of parity results (hopefully)
Updates to text (hopefully early in the week rather than later)
- issues of presentation can be dealt with between the
submission deadline and the Tokyo meeting
April 4 - Submission of vector text for Tokyo
-----Original Message-----
From: Glen Kramer [mailto:glen.kramer@teknovus.com]
Sent: Wednesday, March 26, 2008 10:25 PM
To: Frank Effenberger; Kozaki.Seiji@AB.MITSUBISHIELECTRIC.CO.JP;
wkleung@huawei.com; Eric Lynskey; Marek Hajduczenia; Marek Hajduczenia;
Ryan Hirth; Jeff Mandin; uematsu903@OKI.COM
Subject: ad hocs for April
Dear ah hoc leaders:
I am requesting you to make announcements of your planned activities on
the reflector, outlining the issues to be solved and plan of work.
1) Damage threshold values ad hoc - Frank Effenberger
2) Mathematical analysis of impact of FEC codeword invalidation
- Expected post-FEC BER - Seiji Kozaki
- Probability of receiving a corrupted frame - Raymond Leung
(tentative)
3) Analysis of Tx and Rx PCS delay - Eric Lynskey
- Impact of IDLE insertion
4) Clause 64 ad hoc - Marek Hajduczenia
5) Jitter ad hoc - Ryan Hirth
6) FEC test vectors - Jeff Mandin
7) Power saving proposal - Kiyoshi Uematsu
Thank you,
Glen