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[10GMMF] (10GMMF) revised task 2 and 4 minutes for 1 Dec 04




To follow up on my action item from the Dec 1 Task 2 & 4 call, I would like to express my thoughts on the need for characterizing an EDC-based receiver for dynamic channel response.  An associated thread has been exchanged between Sudeep and Stefano regarding TP3 testing, which I have copied below for reference.  In this excerpt, Stefano states that he has experimentally observed instability in EDC response to changing channels.  He describes it as a divergence from stable minimum mean square error (MMSE) induced by dynamic channel IPR.  
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On Dec 3 2004, Stefano Bottacchi wrote:

Sudeep,

Thank you for your kind response. Please find my comments in line
highlighted in blue.

In addition I would like to rise one flag:

Measurements show 300 meters can be reached under EDC based quite lab
conditions. Polarization changes induced by source fluctuation and
mechanical vibrations set dramatic changes in pulse response starting
after 150 meters length. This is experimentally proved. My question is
the following: the dynamic adaptation capability of MMSE should take
with appropriate time constant and I guess this is achievable (10ms to
100 ms would be enough for tracking temperature and mechanical stress
induced fluctuations). My concern regards instead the MMSE capability to
track the stable convergence minimum when pulse changes occurs under
limiting compensation conditions. This would be quite usual for 300
meters link length. Increasing the number of taps, increase the
available number of MMSE minima for convergence and the algorithm easily
jump out from previous stable condition. This too has been
experimentally demonstrated. I guess TP3 stress test should account for
this.

Best regards

Stefano

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I believe there is also another mechanism that could cause bit errors due to channel dynamics, which may provide insight into how to test for dynamic channel behavior.  The optimal operation of a sampling circuit depends on the stability of its reference clock.  Clock recovery from waveforms as dispersed as those created in 802.3aq channels of interest is no easy task, meaning that it might not be done optimally by all EDC device suppliers.  Spectral and/or temporal information is used to recover and stabilize the clock.  It follows that changes in the temporal or spectral information will cause the clock recovery circuit to adjust its phase.  For example, if the clock were locked to the peak amplitude position of a waveform, and that waveform changed such that the peak shifted in time, then the clock edges would also shift in time within the waveform, resulting in samples from different locations of the waveform.  For an EDC device, the coefficients of the taps would need to be adjusted correctly as the clock shifted.   While it is understandable that the clock recovery circuit can easily track changes at 10s of Hz, Stefano's note indicates that the EDC device may not necessarily properly adjust its tap coefficients with sufficient accuracy and speed to track and the changing waveform without generating bit errors.   If the clock phase is also adjusting in response to the IPR dynamics, this compounds the potential problem.  

Given his experimental observations, it becomes necessary to measure the dynamic behavior of the EDC-based receiver.     A TP3 test wherein the input IPR changes its peak amplitude position at a rate of about 10 to 20 Hz might be sufficient to determine if the receiver will deliver the target BER under dynamic channel conditions.  The simplest waveform that can accomplish this would be a two peaked IPR (with peaks separated by perhaps 600 ps for a 300 m channel, or whatever represents worst-case behavior) where the peak amplitude alternates between the two positions at 10s of Hz.   One would apply this dynamic IPR during the stressed receive sensitivity test.  

Regards,
Paul Kolesar
SYSTIMAX® SOLUTIONS
1300 East Lookout Drive
Richardson, TX 75082
Phone:  972.792.3155
Fax:      972.792.3111
eMail:   pkolesar@systimax.com