RE: 10G-BASE-T question (dd1)

["Grow, Bob" <bob.grow@xxxxxxxxx>]

Tripathi:

I didn't endorse an 8-bit interface in my message.  If you look at my
presentation from last week, you will see that I express similar concerns
about the technology limitations of an 8-bit interface.  My point was that
an 8-bit interface is defined in the GMII and that clock changes would be
obvious.  (In other words, we don't need to define a new 8-bit interface if
the group wants one, just adapt the existing one.) I see no relevance to a
speed independent MAC, Clause 4 specifies a bit serial MAC (implementation
widths of course vary). I don't think it was a problem for gigabit MAC
implimenters to use a 16- or 32-bit internal word with an 8-bit GMII data
path.

--Bob Grow

-----Original Message-----
From: Devendra Tripathi [mailto:devendra.tripathi@xxxxxxxxx]
Sent: Tuesday, June 08, 1999 11:22 AM
To: Grow, Bob
Cc: stds-802-3-hssg@xxxxxxxx
Subject: RE: 10G-BASE-T question (dd1)



> all that need
>change is the clock rate (not something subject to discriminatory
>licensing).  

Bob,

8 bit interface would be very difficult to implemnet at MAC level
at least with current (and probably of two more years) CMOS technology. I
think
the suggestion of 32/8 is in line. The starting PHYs could take 32 bit data
and later on we
could move to 8 bit (may be in next 3-4 years). This is in line with speed
independent MAC too.
We could specify the lower 8 bits of 32 bit to be used in later mode (if
and when that is
implemented).


>A wider interface presents more constraints, and if wanted as
>an option must be used in evaluating a number of the PHY proposals. (A
wider
>interface can affect preamble, IPG, and latency at a minimum.)


I do not see this a problem at least upto 32 bit. Please note that even at
GMII, I am doubtfull
if any one implements internal logic at 125 MHz. Mostly it 16 bit bus
running at 62.5 MHz. At 32
bit we have 3 clocks of IPG and 2 clocks of preamble, both being integers.


Tripathi.

>
>--Bob Grow
>
>
>-----Original Message-----
>From: Dan Dove [mailto:dan_dove@xxxxxx]
>Sent: Tuesday, June 08, 1999 9:22 AM
>To: stds-802-3-hssg@xxxxxxxx
>Subject: Re: 10G-BASE-T question (dd1)
>
>
>
>Hi Jaime,
>
>Actually, I would be happy if we architected a solution that allowed us
>to set the width/clock-rate at initialization. This way, we could use
>a 32 bit wide implementation in early implementations, and possibly an
>8 bit wide implementation later. Whether this is a hard configuration or
>negotiable via MDIO/MDC is negotiable.
>
>My primary concern is that we not standardize an obsolete technology
>that ends up being superceded by a proprietary implementation that
>does not have the rigorous design, or non-discriminatory licensing of
>an IEEE standard.
>
>I believe a small amount of foresight in the development of this 
>standard will save us a lot of pain in the future.
>
>Best Regards,
>
>Dan Dove
>
>-- 
>___________     _________________________________________________________
>_________    _/    ___________  Daniel Dove         Principal Engineer __
>_______     _/        ________  dan_dove@xxxxxx     LAN PHY Technology __
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>_____   _/  _/ _/_/_/   ______  Roseville, CA 95747-5555               __
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>_______      _/      _________  Fax  : 916 785 1815                    __
>__________  _/ __________________________________________________________
>
>kardontchik.jaime@xxxxxxxxxxx wrote:
>> 
>> Rogers,
>> 
>> The figure on page 4 emphasizes more the maximum clock used in the
>> 10G-BASE-T architecture, 1.25 GHz, and the maximum baud rate
>> in the optical fiber, 1.25 Gbaud/sec.
>> 
>> The actual width of the MII interface is a question open to discussion.
>> 
>> Shimon Muller (Sun) suggested using a 32-bit wide interface (64-bit
>> wide if we include both the Tx and Rx). Dan Dove (HP), in the audience,
>> suggested that if we use a 32-bit wide interface we might end up with
>> a chip that is all I/Os surrounding a tiny design, and he suggested to
>> take here an agressive approach and stick to an 8-bit wide interface.
>> 
>> I tend to agree with Dan for the same reason and for another one:
>> 32 TTL-type output drivers at the Rx would introduce a lot of
>> switching noise that could affect the analog blocks in the chip,
>> including the jitter of the transmitter.
>> 
>> Jaime
>> 
>> Jaime E. Kardontchik
>> Micro Linear
>> San Jose, CA 95131
>> email: kardontchik.jaime@xxxxxxxxxxx
>> 
>> "Rogers, Shawn" wrote:
>> 
>> > Jaime, I have a question concerning your presentation in Idaho.  On
page
>4
>> > of your presentation you state the following when comparing your
>10G-Base-T
>> > proposal to 802.3ab (1000Base-T):
>> >
>> >    1000Base-T           10G-Base-T
>> >     GMII-8bit wide      10GMII - same
>> >
>> > Are you advocating a byte wide chip-to-chip interface between the PCS
>and
>> > Reconciliation sublayer in the MAC running at 1.25Ghz?
>> >
>> > Regards,
>> > Shawn
>> >
>> > -----Original Message-----
>> > From: Jaime Kardontchik [mailto:kardontchik.jaime@xxxxxxxxxxx]
>> > Sent: Monday, June 07, 1999 5:57 PM
>> > To: stds-802-3-hssg@xxxxxxxx
>> > Subject: 10G-BASE-T presentation
>> >
>> > Hello 10G'ers,
>> >
>> > For those that were not able to attend the Idaho meeting:
>> >
>> > The presentation on the 10G-BASE-T architecture given
>> > in Idaho included more material than the original posted
>> > two weeks ago.
>> >
>> > The updated presentation as given in Idaho is now in the
>> > web site,  replacing the old one:
>> >
>> > http://grouper.ieee.org/groups/802/3/10G_study/public/june99
>> >
>> > Jaime
>> >
>> > Jaime E. Kardontchik
>> > Micro Linear
>> > San Jose, CA 95131
>> > email: kardontchik.jaime@xxxxxxxxxxx
>
>