Re: 10G-BASE-T question (dd1)

[Denis Beaudoin <dbeaudoin@xxxxxx>]

Devendra Tripathi wrote:

snip...
> 
> >A wider interface presents more constraints, and if wanted as
> >an option must be used in evaluating a number of the PHY proposals. (A wider
> >interface can affect preamble, IPG, and latency at a minimum.)
> 
> I do not see this a problem at least upto 32 bit. Please note that even at
> GMII, I am doubtfull
> if any one implements internal logic at 125 MHz. Mostly it 16 bit bus
> running at 62.5 MHz. At 32
> bit we have 3 clocks of IPG and 2 clocks of preamble, both being integers.
> 
> Tripathi.

Tripathi, 

  I just wanted to point out that all the GIG MACs we have implemented used an
8 bit data path. The current CMOS technology easily runs at 125-150Mhz. I 
myself have put 8 GMII interfaces on one device (256 pins), all running
at 125Mhz with 8 bit data paths. We also used 125Mhz as out internal working
clock as well.

Denis

> 
> >
> >--Bob Grow

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