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Re: Hari




Hi Dan,

Please allow me to poke a bit into your comments (below):

"DOVE,DANIEL J (HP-Roseville,ex1)" wrote:

> Hi Rich,
>
> Actually, I have to disagree with your relation of HARI to the TBI.
>
> I believe that the un-specified SERDES interface is a more appropriate
> model as it is;
>
> a) Differential
> b) High Speed
> c) Asynchronous (ie: Clocks are derived rather than sent discretely)

All the above remains the same for each Hari lane as well as Hari, which is the
combination of all lanes as a parallel-serial bus

> However, the industry might have gained from standardization of that
> interface. If you are aware (and I am sure you are) there are now AC
> coupled and DC coupled versions of the SERDES interface that just
> complicate board designs.

It sounds like Hari Electrical has chosen AC coupling only. In that case, DC
coupling would not be compliant nor work, especially if caps are required at
both ends. I didn't see this in the Kauai presentations, but I believe that this
is part of the Hari baseline. Other should feel free to challenge or support
this assertion.

> I support the HARI concept, although I believe that we need to work on
> it a bit to understand the impact of splitting the 8B10B codes onto
> separate channels will have.

Really the only major issue is how to deskew the lanes and where the deskew
function is performed. 8B/10B codes really can not/should not be split into a
finer granularity than 10-bit code-groups. I believe that you did not intend
otherwise. So the only remaining issue is whether or not there is any
requirement to block code-groups beyond a granularity of one on each
channel/lane. Hari proposed for 10 GbE and InfiniBand blocks with a granularity
of one code-group. My prejudice is to perform lane deskew in the SerDes. This
would result in an additional item (d) in your list above which would be
pertinent to Hari SerDes but not the TBI.

> As for Roy's concerns about that interface complicating things, I
> believe that concern is resolved (or should be) by the fact that HARI
> would at most be an optional interface.

Agreed.

Best regards,
Rich

 --

> Best Regards,
>
> Dan Dove
>
> PS: Have a nice Thanksgiving
>
> ___________     _________________________________________________________
> _________    _/    ___________  Daniel Dove         Principal Engineer __
> _______     _/        ________  dan_dove@xxxxxx     LAN PHY Technology __
> _____      _/           ______  Hewlett-Packard Company                __
> ____      _/_/_/ _/_/_/  _____  Workgroup Networks Division            __
> ____     _/  _/ _/  _/   _____  8000 Foothills Blvd. MS 5555           __
> _____   _/  _/ _/_/_/   ______  Roseville, CA 95747-5555               __
> ______        _/      ________  Phone: 916 785 4187                    __
> _______      _/      _________  Fax  : 916 785 1815                    __
> __________  _/ __________________________________________________________
>
> -----Original Message-----
> From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> Sent: Friday, November 19, 1999 12:47 AM
> To: HSSG
> Subject: Re: Hari
>
> Roy,
>
> I thought that Hari was clearly presented in at least half a dozen
> presentations by at
> least the same number of presenters who all explained it in the same way in
> Kauai. I'll
> try one more time here.
>
> Hari is the same as the Serial interface of the 10 GMII as presented to the
> HSSG by
> Howard Frazier of Cisco in Montreal, York and Kauai. A group of Ethernet,
> Fibre Channel,
> InfiniBand and even OIF folks have gotten together over the past several
> months to try
> and arrive at a common interface for passing 10 Gbps of data continuously in
> each
> direction between a PCS/PMA element (which may be integrated with the MAC
> and the PMD
> (i.e. transceiver module).
>
> Note that a typical Ethernet PHY, like 1000BASE-X contains the PCS, PMA and
> PMD
> sublayers. Hari is NOT a PHY nor is it a PHY sublayer. Hari is an interface
> between
> sublayers and is very similar in nature to the Ten-Bit Interface (TBI) of
> 1000BASE-X,
> which is fully described in Clause 36 of that standard.
>
> Hari has nothing at all to do with WWDM although it clearly may be used to
> attach a WWDM
> PMD to its MAC/PCS/PMA.
>
> Hari may be used to attach a Parallel Optical PMD to its MAC/PCS/PMA in much
> the same
> fashion as for WWDM
>
> Hari usage to attach a MAS PMD to its MAC/PCS/PMA has been described in all
> my MAS
> proposals to the HSSG including the latest update presented in Kauai:
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/taborek_2_1199.p
> df
>
> Hari usage to attach a Serial PMD to its MAC/PCS/PMA along with a proposed
> coding to
> maintain a line rate of ~10 Gbaud has been described in the Kauai proposal
> by Rick
> Walker and Richard Dugan of Agilent:
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/walker_1_1199.pd
> f
>
> Therefore, Hari provides a common interface for all major classes of PMDs
> proposed to
> the HSSG to date in addition to being strongly considered as a common
> interface for
> other ~10 Gbps standard and industry interfaces.
>
> The principal strengths of Hari are:
> 1) Low pin count
> 2) Self-timed (doesn't need a clock with data)
> 3) Supports reasonable distances over inexpensive medium (e.g. 20" of FR4
> traces)
> 4) Good synergy with traditional Ethernet MAC/PHY framing
> 5) Sufficient robustness to not compromise a 10E-12 link BER
>
> 8B/10B encoding has been proposed for Hari since it has been proven time and
> time again
> in multiple forums that 8B/10B is a very robust serial link transmission
> code. However,
> Hari is not a PCS and an alternate code could have been proposed for Hari. I
> consider
> the Hari usage of 8B/10B to be analogous to a parity bit for a traditional
> parallel
> interface. The "parity bit" can be generated at the source and discarded
> after checking
> at the destination. The MAS and Serial PMD proposals referenced above use
> Hari in
> exactly this fashion and result in the lower line rate possible for those
> respective
> interfaces when compared to a PMD coding which would carry forward the
> 8B/10B overhead.
>
> Hari is being proposed for inclusion into the 802.3ae standard as an
> interface as
> described above. However, Hari does not dictate the encoding of data
> transported over
> the Medium. Hari simply enables the transport of that data over the medium
> in a manner
> commensurate with the 5 criteria of 802.3ae.
>
> As such, I would also recommend that Hari be considered for the WAN PHY.
>
> Best regards,
> Rich
>
> --
>
> Roy Bynum wrote:
>
> > Rich,
> >
> > I am confused here.  Is Hari being proposed as a PHY for the LAN
> compatible PHY of
> > 10GbE?  I have recognized that Hari only needs the WWDM optical interface
> to be a 4
> > wavelength parallel short reach PHY.  When it was first presented, the way
> that it
> > was presented reminded me of a "solution looking for a problem".  It
> certainly looks
> > like there are a lot of people have been working on this for some time.
> All of the
> > conversations on the reflector are starting to treat Hari as a PHY, not a
> device
> > interconnect.  I am confused why an interconnect suitable to be a full LAN
> PHY would
> > be proposed first as a device interconnect.  As a 500m  and less LAN PHY,
> I am
> > neutral on Hari.  As something else, I confused by the way it was
> presented and have
> > my doubts as to the overall impact of Hari as a device interconnect and
> the
> > limitations that it inherently makes on the PCS/PMD relationship.
> >
> > Hari as a device interconnect requires specific functionality.  It forces
> the
> > physical coding functionality of non parallel PHYs to exist at the PMD,
> not the
> > PCS.  I have been told by a Hari supporter that the PCS/PMA/PMD
> relationship is
> > purely for the standard and has little relationship to how protocols are
> implemented
> > and devices are actually designed.  If device and protocol implementation
> has little
> > to do with the standard, why have the standard?  If the protocol
> implementation is
> > specific to the standard, then Hari is a PCS specific to a particular PHY
> and is
> > exclusive of other PCS definitions for other PHY definitions.
> >
> > If Hari is a PCS, let us recognize it as such and move on with other PHY
> > definitions.  If it is not a PCS then let us recognize that it will alter
> the nature
> > of the relationships of the PHY functionalities for the non-WWDM PHYs
> dramatically.
> > A silicon designer can best determine if the increase in complexity of the
> PMD is
> > countered by the pin count benefits of Hari as something other than a PCS.
> Hari as
> > a device interconnect needs to be removed from the table.  Hari as a PCS,
> with minor
> > modifications can be evaluated as such.
> >
> > Thank you,
> > Roy Bynum
> >
> > Rich Taborek wrote:
> >
> > > The purpose of this note is to clear up confusion regarding Hari, a
> > > proposed 4-lane serial interface for 10 GbE and train-up sequences.
> > >
> > > It should be clear that NO TRAINING SEQUENCES are proposed for Hari.
> > > Both the "Hari Coding Objectives" presentation
> > >
> (http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/taborek_1_1199.
> pdf)
> > > and "Word Striping on Multiple Serial Lanes"
> > >
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/ritter_1_1199.pd
> f)
> > > make a point of noting that no train-up is required Hari to deskew.
> > >
> > > The Hari Coding Objectives proposal uses the standard Idle sequence
> > > proposed by Howard Frazier of Cisco to deskew multiple parallel lanes
> > > while simultaneously acquiring code-group synchronization on all lanes.
>
>   ----------------------------------------------------------
>
> Richard Taborek Sr.   1441 Walnut Dr.   Campbell, CA 95008 USA
> Tel: 408-370-9233     Cell: 408-832-3957     Fax: 408-374-3645
> Email: rtaborek@xxxxxxxxxxxxx

 ----------------------------------------------------------

Richard Taborek Sr.   1441 Walnut Dr.   Campbell, CA 95008 USA
Tel: 408-370-9233     Cell: 408-832-3957     Fax: 408-374-3645
Email: rtaborek@xxxxxxxxxxxxx