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Re: Hari


Dan,

Please let me comment on a couple issues in this thread.

Regarding DC vs. AC coupling, my understand of what gets in the way
of DC coupling is the varying DC levels sent and expected by the
various serdes.  Particularly, PECL and CML levels are incompatible.
Even using a single serdes family, power domains might be a problem 
for DC coupling.

Regarding 8b10b disparity, even though it is maintained on each
HARI lane in both the proposed coding schemes, don't be too quick
to assume there's no problem.  Some coding schemes have proposed
patterns that cause disparity problems.  Also, PMDs that interleave
the four streams into a single 8b10b stream need to adjust the
coding for correct disparity.  The first reference below (coauthored
by Al Widmer) points out that this can be done without the need
for the heavy logic of decode/encode.

Lastly, regarding deskew, the word striped coding scheme (ref #1 
below) requires NONE, significantly simplifying the implementation.
The reason is because a word at the lane rate is 12.8 ns while
the max skew is on the order of 6 ns, so a word clock from any lane 
can latch the words from all lanes.  Byte striping, by contrast,
will require high clock rates and much more complex operations
that will need to span all the lanes.  LSI Logic's serdes, and
to my understanding most other serdes designs, are not compatible
with byte striping (both refs below).

Regards,
Mike

http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/ritter_1_1199.pdf

http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/jenkins_1_1199.pdf
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