Re: Hari
Mike,
A few comments on Disparity and Byte vs. Word Striping
Mike Jenkins wrote:
> <stuff deleted>
>
> Regarding 8b10b disparity, even though it is maintained on each
> HARI lane in both the proposed coding schemes, don't be too quick
> to assume there's no problem. Some coding schemes have proposed
> patterns that cause disparity problems. Also, PMDs that interleave
> the four streams into a single 8b10b stream need to adjust the
> coding for correct disparity. The first reference below (coauthored
> by Al Widmer) points out that this can be done without the need
> for the heavy logic of decode/encode.
I don't advocate any 8B/10B-based coding schemes which compromise the Running
Disparity error control feature of that code. Note that in a Byte-Striped Hari,
Running Disparity is ALWAYS processed separately for each lane. Note also such
processing may be implemented at virtually any reasonable rate including 12.8 nsec
(40-bit words).
LAN PHY Serial PMDs that interleave the four streams into a single 8B/10B stream
need to adjust the coding for correct disparity AND operate at the high line rate
12.5 Gbps to transport 10 Gbps of Ethernet data. An alternate Serial PMD that has
been proposed by Rick Walker and Richard Dugan of Agilent in Kauai, supports Hari
and its 8B/10B steams at the Serial 10 GMII and then recodes the data as a 64B/66B
stream resulting in the transport of 10 Gbps of Ethernet data at the more
reasonable line rate of 10.3125 Gbps, allowing the use of virtually all existing
OC-192 class optoelectronic components.
> Lastly, regarding deskew, the word striped coding scheme (ref #1
> below) requires NONE, significantly simplifying the implementation.
> The reason is because a word at the lane rate is 12.8 ns while
> the max skew is on the order of 6 ns, so a word clock from any lane
> can latch the words from all lanes. Byte striping, by contrast,
> will require high clock rates and much more complex operations
> that will need to span all the lanes. LSI Logic's serdes, and
> to my understanding most other serdes designs, are not compatible
> with byte striping (both refs below).
Hari word-striping requires that lane deskew be performed past the Hari receiver's
deserializer, requiring significant additional high-speed logic. It is true that
lane deskew may be performed for "free". However, what is certainly not free are
the large high-speed FIFOs to accumulate full words from the deserializer on all
lanes prior to processing the words. Other disadvantages of word-striping include:
- A more complex and potentially protocol dependent means of performing clock
tolerance compensation. Insertion/Removal of words by a PMD must be performed by
searching for specific 40-bit Ordered-Sets, possibly hundreds of them rather than
locating a simple column of /K/s or /R/s for the byte-striped approach.
- Word striping automatically incurs significant latency for all low-latency Hari
applications (e.g. InfiniBand, etc.) due to the inability to use any data until a
word is completely received in each lane;
Hari byte-striping allows any application to transport data at the lowest latency
afforded by 8B/10B code and allows multi-lane deskew to be
performed simultaneously with code-group alignment in the Hari receiver's
deserializer. Subsequent to deserialization 40-bit column and code-group aligned
data, 10-bits per lane, are passed at a 3.2 nsec rate to the next level of receive
logic. With this design, Hari is truly
independent of lane data blocking beyond the code-group level and there are NO
running disparity twister games to play.
No additional logic is required to deskew lanes past the deserializer and simple
logic may be employed to insert/remove R columns in the PMD in a truly protocol
independent manner.
> Regards,
> Mike
>
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/ritter_1_1199.pdf
>
> http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/jenkins_1_1199.pdf
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Mike Jenkins Phone: 408.433.7901 _____
> LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R)
> 1525 McCarthy Blvd. mailto:Jenkins@xxxxxxxx | |
> Milpitas, CA 95035 http://www.lsilogic.com |_____|
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
Best regards,
Rich
----------------------------------------------------------
Richard Taborek Sr. 1441 Walnut Dr. Campbell, CA 95008 USA
Tel: 408-330-0488 or 408-370-9233 Cell: 408-832-3957
Email: rtaborek@xxxxxxxxxx or rtaborek@xxxxxxxxxxxxx