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HSSG,
Looks like I finally decided to check into the conversation at an exciting point. It's probably a good thing that I'm going on vacation for a week so I can't see the repercussion. My intent in this e-mail is only to say what I've already done in order to meet my system design requirements, for better or for worse.
Before I knew anything about the HSSG (June '98), I started a systems company with the objective to send as many packets over a backplane as possible (and subsequently over fiber(s), of course). I think that this goal is substantially in line with the basic tenets of HSSG.
I have three objectives in building my system: 1) bidirectional, redundant 10Gbps throughput per line card to my core switch fabric (we have two, redundant core fabric cards and 16 line cards), 2) smallest possible size, and 3)low cost. I think that 2) and 3) are in line with industry-wide desires.
I've been a systems designer for a couple of decades, and, like Roy, I say the tighter the better. So, after surveying the available components, and I looked at MANY, I decided to go with the MxNxGbps 8B/10B transceivers where N is the data rate multiple {N=1.0, 2.0, and soon to be 2.5} and M is the number of transceivers per package {M=1,2,4}.
Here's why. My backplane must support 32 bidirectional 10Gbps links with cards that are the vertical height of Compact-PCI cards. If you do the math you'll find that there just isn't any easy way (using off the shelf connectors, e.g., 2mm family) to get 32 bidirectional 10Gbps channels across a 10.5" high FR4 backplane unless you go with 4 2.5Gbps serial channels per 10Gbps channel. Much of the reason it is hard to fit is that you need 4 ground/shield pins per channel to make it across the connector without destroying signal integrity. This decision is a result of the physical size constraint of the system which was fairly immutable in my case. In addition, I don't have a lot of board space reserved for the backplane interconnect---I want to use every sq. in. of real estate for silicon that adds value to the packets i.e., routing, classifying, filtering, QOS, etc. It's very tight. Off-the-shelf 4-channel (with 4 redundant channels) 8B/10B ENDEC that only requires 1.4 sq. in. of board real estate. That's a very tight package. I have not been able to find a similarly sized 4xOC48 (with all ports redundant) chip. If any one has one, please let me know.
Now, what about the cost?
I'm certainly not in love with 8B/10B from the bandwidth efficiency standpoint (to put it bluntly, it sucks). So I too dreamed up various 16B/18B, 32B/34B, 64/66B ideas. But these are untried, unproven and certainly not off-the-shelf. Sure, I could also have decided to go with the X^43+1 scrambler but the only off-the-shelf stuff I can find has SONET framing. But I just can't see paying for all that framing logic If I just need to get a packet over 20" of FR4. Good system designers stick to the KISS principle. So 8B/10B was chosen. Fortunately 8B/10B has some other major strong points in addition to being tried and proven. It has shipped in very high volume and thus it is inexpensive; second, when it comes to Silicon, you just can't get much more efficient than 8B/10B. Moreover, it takes very few gates to implement an interface to an 8B/10B ENDEC---such an interface can easily be done in Xilinx Virtex FPGAs. This is important because FPGA's make it easier get to market fast which is the whole point. Most importantly, what I really like about the new flavors of multi-gigabit multi-xcvr 8B/10B ENDECs is that there are multiple vendors and the pricing is in tune with the LAN. Thus I can meet my cost objectives, my time-to-market objectives and I have an upgrade path as the XCVRs scale in speed.
So, while I have not made any decisions with respect to HARI and it's complexities, I'm definitely sold on a 4-channel 8B/10B 2.5Gbps(3.125Gbaud) serial coinnection across an FR4 backplane, for what it's worth, since I've already built the darn thing!
Regards,
Charles Barry