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Re: Hari

Paul,

I'll intersperse my comments below:

Paul Bottorff wrote:

Rich:

I agree that Hari was clearly presented. I also question whether the
architectural model  in use for Hari is rational.

Another way to look at Hari is as a PMD for the LAN PHY. It is basically a
20 inch medium dependent interface. With this outlook the Hari PMD is then
mapped to other PMDs using something I we might call an L1 translator. The
resulting systems using this model are just like the ones presented for
Hari, but give a much better understanding of how the architecture is
mapping to the layers.

Me thinks it best to stick with 802.3 layer models for 802.3 projects. The resultant layers, including the position of Hari in the stack can be illustrated as follows. Note that Hari is not a PMD, rather it is an interface between the PHY's PMA and PMD sublayers:

                        802.3ae
                      Full Duplex
                        Layers

      |              Higher Layers              |
      +-----------------------------------------+
      |       LLC - Logical Link Control        |
      +-----------------------------------------+
      |         MAC Control (Optional)          |
      +-----------------------------------------+
      |       MAC - Media Access Control        |
      +-----------------------------------------+
      |             Reconciliation              |
      +-----------------------------------------+
      |       LLC - Logical Link Control        |
      +-----------------+---+-------------------+
                        |   | Parallel 10GMII (Optional)
      +-----------------+---+-------------------+
      |     PCS - Physical Coding Sublayer      |
      +-----------------------------------------+
      |    PMA - Physical Medium Attachment     |
      +-----------------+---+-------------------+
                 (Hari) |   | Serial 10GMII (Optional)
      +-----------------+---+-------------------+
      |     PMD - Physical Medium Dependent     |
      + - - - - - - - - - - - - - - - - - - - - +
      |  PMDC - PMD Coding Sublayer (Optional)  |
      + - - - - - - - - - - - - - - - - - - - - +
      | PMDA - PMD Signaling Sublayer (Optional)|
      +----+---------+-----------+---------+----+
           | LX PMD  |           | SX PMD  |
           +-+-----+-+           +-+-----+-+
             | MDI |               | MDI |
           +-+-----+-+           +-+-----+-+
           | Medium  |           | Medium  |
           +---------+           +---------+

Using this model we see that Hari as presented relies on an 8b/10b PCS
associated with the MAC. This means Hari connects to an 8b/10b PCS (perhaps
the LAN PHY) on the MAC side. The L1 translator on the other side converts
the Hari PMD + LAN PHY to an alternate PMD + PHY. The transform required at
the translator depends on which PMD/PHY we are mapping Hari into.
I agree with your description above. For WWDM and Parallel PMDs, 8B/10B may be passed across the PMD to the medium. Alternatively, these PMDs as well as Serial and MAS PMDs may strip the 8B/10B code and recode within the PMD.
When the translation between PMDs is within the same PHY family (LAN PHY to
LAN PHY) then no code translation is required, even though the translator
still needs deskew, reclocking, and rate matching buffer.
It seems to me that your model is starting to get unnecessarily complex. For example, the optional Hari could instead be an optional 16-bit parallel interface as is the case for SONET. However, I may be missing something in your description. Only like PHY's and like PMDs within the same PHY family can communicate. Otherwise, they must be bridged.
When the translation between PMDs is between a LAN PHY and a WAN PHY, then
there needs to be a method to slow down the data rate delivered over Hari
so the L1 translator will not require an entire switch buffer (like 16
Mbytes) for the rate match. Both WORD HOLD and IPG stretch techniques could
be used here. The WORD HOLD could be implemented using the same scheme we
suggested for the XGMII by adding a HOLD signal to Hari and by finding a
control code to represent the NULL.
I believe that this translation between PMDs of a LAN PHY and a WAN PHY is called bridging. I agree with your direction to use Hari control code to to this. It is possible that the proposed Insert/Remove code is sufficient.
Overall the Hari interface adds the L1 translator logic to a design. Though
this may be useful for some designs it is a lot of baggage to carry when it
is not necessary. For many switches the MAC/PHY/PMD are co-located on the
board and an Ethernet backplane extension just adds complexity.
Hari addresses the significant distances between MAC/PCS/PMA chips and PMDs for most multi-port switches/routers which are very difficult to address with a non-serial interface. Do you have any alternative suggestions. Hari does add a bit of complexity, but I believe that this is a good cost-performance tradeoff in light of all the benefits Hari provides.
The biggest issue with Hari is that it does not provide a universal
interface for PMDs. A PMD for the WAN PHY using Hari will be different from
a PMD for the LAN PHY using Hari.
Hari as an optional interface best addresses common PMD interface requirements for most, if not all, LAN PHY PMDs. It may not be the best choice for the WAN PHY, but I believe it is a workable choice and can't think any better universal PMD interface. Can you?

Best regards,
Rich

--

Cheers,

Paul

  ----------------------------------------------------------

Richard Taborek Sr.   1441 Walnut Dr.   Campbell, CA 95008 USA
Tel: 408-330-0488 or 408-370-9233           Cell: 408-832-3957
Email: rtaborek@xxxxxxxxxx or rtaborek@xxxxxxxxxxxxx