Re: HARI: Question regarding byte (column?) versus word striping
Jeff,
Let me try to answer some of your concerns regarding word striping.
Also, I loved your four-lane-highway analogy to explain lanes and
striping, so I will try to build on it.
> I'm already having trouble with the idea that I have to create a
> word stream clocked at 4x the speed of a link,
> just to be able to cross my clock boundary. (Please reference my
> previous e-mail of 06 Jan for details.)
Below is a description of a word striped HARI interface which
reuses existing designs. It does the speed matching separately
in each lane as you have expressed a preference for. I believe
this is functionally identical to the diagrams in Mark Ritter's
presentation, but is more similar to the gigabit devil we know:
_________LANE 3_______________________________
| _________LANE 2_____________________________|_
| | _________LANE 1_____________________________|_ __
> | | _________LANE 0_____________________________|_ ======>| \
| > | | __________ __________ __________ | ====>|MUX\==>
| | > | | | | | | | | ==>| /
| | | >->| DESER. |==>| FIFO |==>| DECODE |==>=======>|__/
| | | | |__________| |__________| |__________| | __
< | | | | <======| \
| < | | __________ _ __________ | <====|DE \<==
|_| < | | | / | | | | <==|MUX/
|_| <--|SERIALIZER|<======| |<======| ENCODE |<========<=|__/
|_| |__________| \_| |__________| |
|______________________________________________|
* Control logic across four lanes determines when to add/delete a
"skip" word in one FIFO for speed matching. For delete operation,
the normally rotating MUX address skips that lane. For an add
operation, the MUX address dwells on that lane for two words.
(This logic is identical to existing control logic for speed
matching buffers with the four FIFOs viewed as one address space.)
>
> Now you are saying that if the skew spec changes, I will have to
> change the size of my internal data path. If I understand correctly,
> the clock boundary transition is intended to be done at the word
> size, whatever that may be.
No, I'm not saying that. First, no scheme will work for
arbitrarily large skew. The internal data path width is
not necessarily the same as the word length. A word
striped design could be modified to accommodate increased
skew in a way that was transparent to the higher protocol
(except, possibly for increased latency). I can't say how
a byte striped design could be modified, since I don't
understand in detail how it deals with the present skew spec
(but I'm sure it would also involve extra latency).
>
> I have a hard time understanding how this can be simpler. Column/byte
> striped skew compensation does not seem like a picnic either, but
> I believe a change there would impact state machines and buffer depths,
> but leave my internal data path widths intact. Word striping would
> seem to affect all three, in that case.
>
> I am trying to think of ways to avoid having to create that word
> stream... the problem is, the single idle word could appear on any
> lane, and might -never- appear on a lane... anything I have been
> able to think of (so far) has been too complicated for my taste.
>
> Please help me understand what I am missing... thanks! - js
Jeff, this is answered in the bullet below the diagram above.
In word striping, the FIFO fullness adjustment for all lanes
is accomplished by adding/deleting a word in ANY SINGLE LANE.
To extend your four-lane analogy, the FIFOs are the lines of
vehicles waiting at the toll booths in all four lanes. Say
there is only one toll booth attendant, and he goes to each
lane in turn to collect a fare and let the vehicle through.
(This is the MUX in the diagram above.)
If he periodically looks up and sees the lines are too long,
he waves a vehicle in one lane through without taking the
time to collect the toll and continues on his rounds. All
four lines get a little shorter because he is speeded on his
rounds.
If, when he looks up, he sees there are few vehicles, he
can pause and discuss the weather with one driver. All the
lines now get a little longer because his rounds are delayed.
Please let me know if that does not address your concerns.
>
> jeff stai, QLogic corp.
> 3545 harbor blvd, costa mesa, ca 92626
> 714-668-5425vm, 714-668-5095fx
> j_stai@xxxxxxx http://www.qlc.com/
Lastly, let me extend your analogy one more time. Where
byte striping has one driver in a car in each of the four
lanes, word striping puts the four drivers in a carpool in
stretch limo that is four times as long as their own cars.
Now, the limo riders in lane 1 can look over to lane 2 and
be certain the limo they're looking at is the next in order.
(They can signal each other via the IR port on their Palm
Pilots ;-) In the byte stripe case, their carpool buddy
in the next lane might be two cars up or back. This is the
skew issue.
(Sorry....I guess I'm getting punchy. I'll go home now.)
--
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Mike Jenkins Phone: 408.433.7901 _____
LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R)
1525 McCarthy Blvd. mailto:Jenkins@xxxxxxxx | |
Milpitas, CA 95035 http://www.lsilogic.com |_____|
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