Re: WISardry
Dave,
Good questions. Here are the answers:
1) The WIS, like any other 802.3 PHY sublayer, is bi-directional. In Mr. Paul
Bottorff's, et. al. presentation "10GE WAN PHY Overview",
http://grouper.ieee.org/groups/802/3/ae/public/may00/bottorff_1_0500.pdf, slide
4, the WIS is shown to reside between the 64B/66B PCS and the PMA sublayers. In
this illustration, the "top" of the WIS handle 66B frames and the "bottom" of
the WIS provides an interface to the PMA. The prevalent "PMA" interface for
existing OC-192 products is a 16-bit parallel interface.
On slide 9 of taborek_3_0500.pdf, the "bottom" of the WIS handles 66B frames. I
admit that there is an error in the drawing since a 64B/66B PCS sublayer is
missing. I assume that the 64B/66B sublayer is always present as the PCS for the
WIS. Likewise, slide 10 should show 64B/66B between the XGXS and the WIS.
On slide 9 of taborek_3_0500.pdf, the "top" of the WIS provides a PMA interface
as it does for corresponding illustration of the WAN PHY in bottorff_1_0500.pdf,
slide 4.
The LAN PHY always operates at a 10.0 Gbps line rate regardless of whether the
PHY is configured as an Ethernet-to-Ethernet or Ethernet-to-SONET link. However,
the data rate is different between the two, always less than 10 Gbps due to the
presence of IPG, as well as variable since variable sized packets are allowed.
Rate control increases the IPG to decrease the effective data rate for
Ethernet-to-SONET links.
Open Loop rate control is activated in the MAC on the far left side of
taborek_3_0500.pdf, slide 9 since this link is configured as a Ethernet-to-SONET
link. I should have shown rate control active in this figure. Note that
regardless of the location of the WIS in the link, the WIS must still construct
SONET compatible frames with an SPE filled with 66B words at a rate not
exceeding 9.58464 Gbps with no real guidance from the MAC. Note also that WIS
framing is independent of the rate control methodology (i.e. open loop, busy
idle, etc.).
2) This should be answered in (1) above. The ITU-T side is unaware of the LAN
pacing.
3) I'll have to turn this question around to you since I believe that the
objective of bridging 10 GbE to SONET is to only have to perform SONET framing
once. What is the purpose of a full SONET/SDH framer feeding into the Serdes if
the WIS whether at the end of a LAN PHY or part of a WAN PHY already perform
SONET framing?
Is is for pointer adjustment to account for clock tolerance differences between
the Ethernet and SONET sides only? If this is the case then I consider it an
implementation issue in the WIS to perform the appropriate compatible pointer
adjustment.
I show an empty box between the WIS and the SerDes (ITU-T "PMA") to indicate
that no further reframing is required.
Attachment: I've corrected slides 9 and 10 in taborek_3_0500.pdf and attached
those two slides to this note.
> David Martin wrote:
>
> Rich Taborek,
>
> I have a question for clarification regarding your last presentation in
> Ottawa:
>
> http://grouper.ieee.org/groups/802/3/ae/public/may00/taborek_3_0500.pdf
>
> Looking at slide 9, the "WDM LAN -> WAN" sketch, specifically the left-hand
> stack in the Bridge, with the WIS. The service interface to the WDM LAN
> PCS is the XGMII, which passes MAC frames.
>
> 1. The bottom of the WIS expects/generates SONET-like frames, not MAC
>
> frames. What is the diagram intended to illustrate?
>
> The LAN PCS service interface operates at a 10.0G data rate.
> 2. The service interface of the WIS operates at 9.58464G. Is there an
> assumed
>
> pacing mechanism in the stack?
>
> Referring to the right-hand stack in the Bridge, the ITU-T side.
> 3. If MAC frames are what is passed between the left/right sides, then there
> needs
>
> to be an encapsulation function on the top right with a full SONET/SDH framer
> below it, feeding into the Serdes. Is that what the empty box includes?
>
> ...Dave
>
> David W. Martin
> Nortel Networks
> +1 613 765-2901
> +1 613 763-2388 (fax)
> dwmartin@xxxxxxxxxxxxxxxxxx
>
> ========================
--
Best Regards,
Rich
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Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
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WDM_PCSPMA_RevD.PDF