Re: XGMII
Single Clock ... truely awesome ( Sorry ... best wasn't good enough :):) )
Take care
Joel
---------------
Rich Taborek wrote:
> Single clock, BETTER.
>
> (anyone want to follow with BEST?)
>
> Best Regards,
> Rich
>
> --
>
> "Hakimi, Sharam (Sharam)" wrote:
> >
> > Single clock, GOOD.
> >
> > Sharam
> >
> > > ----------
> > > From: Claus Stetter[SMTP:cstetter@xxxxxxxxxxx]
> > > Sent: Tuesday, July 18, 2000 5:32 PM
> > > To: Roger Ronald; 802.3ae
> > > Subject: Re: XGMII
> > >
> > >
> > > Hi Roger,
> > >
> > > I fully agree with your statement. Why add additional pins to an already
> > > wide interface and add the complication of synchronization when it can be
> > > done with relative ease with a single reference clock? Several companies
> > > that I know of are implementing XGMII as presented and have not had issues
> > > with the proposed timing spec.
> > >
> > > If it ain't broke, don't fix it ;-)
> > >
> > > Cheers,
> > > Claus
> > >
> > >
> > > Claus Stetter
> > > Allayer Communications
> > >
> > > Tel: +1 408 570 0888 x170
> > > Fax: +1 408 570 0880
> > > Cell: +1 408 221 6461
> > >
> > > Email: cstetter@xxxxxxxxxxx
> > > http://www.allayer.com
> > >
> > > ----- Original Message -----
> > > From: Roger Ronald <rronald@xxxxxxx>
> > > To: Justin Gaither <jgaither@xxxxxxxxxxxxxxx>; 802.3ae
> > > <stds-802-3-hssg@xxxxxxxx>
> > > Sent: Tuesday, July 18, 2000 4:26 AM
> > > Subject: Re: XGMII
> > >
> > >
> > > >
> > > > This interface does not seem to be any harder than interfacing to DDR
> > > RAM
> > > > at the same speed. Every corner garage shop will soon be turning out
> > > > DDR RAM based motherboards soon.
> > > >
> > > > Personally, I'd much rather have relatively tight timing instead of
> > > > complications in the clocking and a whole new chip to chip
> > > > protocol to spec/understand/debate/document/build.
> > > >
> > > > RR
> > > > ----- Original Message -----
> > > > From: "Justin Gaither" <jgaither@xxxxxxxxxxxxxxx>
> > > > To: "802.3ae" <stds-802-3-hssg@xxxxxxxx>
> > > > Sent: Monday, July 17, 2000 3:15 PM
> > > > Subject: XGMII
> > > >
> > > >
> > > > >
> > > > > Everyone,
> > > > >
> > > > > Concerning the XGMII interface, I remember at least one comment
> > > > > during the plenary and I have the same reservation concerning the
> > > > > extreme width and tightness of the setup and hold timing.
> > > > >
> > > > > I would like to suggest separate clocks for each of the 8 bit lanes.
> > > > > This would allow each lane to have a manageable number of tightly
> > > > > coupled signals, and allow for 1 or two clocks skew between lanes.
> > > The
> > > > > Bus could easily be spread across the pins of a device enabling
> > > > > distributed reference and less ground bounce. I don't see adding 3
> > > more
> > > > > pins to a 37 pin interface to be excessive. Synchronization of the
> > > > > lanes could be done using the control lines for a sync. (i.e.. 1111
> > > > > followed by 1000 on the control is start of data).
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > Justin Gaither Phone: 512-306-7292 x529
> > > > > RocketChips, Inc. Fax: 512-306-7293
> > > > > 500 N. Capital of TX Hwy.
> > > > > Bldg 3 email: jgaither@xxxxxxxxxxxxxxx
> > > > > Austin, TX 78746 WWW: www.rocketchips.com
>
> -------------------------------------------------------
> Richard Taborek Sr. Phone: 408-845-6102
> Chief Technology Officer Cell: 408-832-3957
> nSerial Corporation Fax: 408-845-6114
> 2500-5 Augustine Dr. mailto:rtaborek@xxxxxxxxxxx
> Santa Clara, CA 95054 http://www.nSerial.com
--
Joel Goergen
Force10 Networks
1440 McCarthy blvd
Milpitas, Ca, 95035
Email: joel@xxxxxxxxxxxxxxxxxxx
Direct: (408) 571-3694
Cell: (612) 670-5930
Fax: (408) 571-3550