Re: Clause 33 comments
Ben,
Thanks for the comments. Here are my responses :
1/ There is no particular reason for this to be limited to the control register
and you are right, all registers should be included. I shall change the text to
the following : "While the reset process is not yet complete, the PMA/PMD is not
required to accept a write transaction to any of its registers."
I think that I also need to change the sentence "This action shall set the
status and control registers to their default states." (line 44) to read "This
action shall set all registers to their default states."
I also need to make these changes to all the other device's 'Reset' paragraphs.
2/ I had intended the link status bit to be the 'de-skewed' indication. I forgot
to include this in the definition !
I shall change the definition to say "When read as a logic one, bit 3.1.4
indicates that the XAUI transmit link is de-skewed. When read as a logic zero,
bit 3.1.4 indicates that the XAUI transmit link is not de-skewed."
If people think that the XAUI link OK function needs further qualification
criteria then I'll make a specific 'de-skewed bit' and re-define the XAUI link
OK bit accordingly.
I also need to make these changes to the DTE XGXS (p83).
3/ For safety I'd say that the address should stick at 65535, and will add this
in on page 84.
4/ I deliberately did not include the MF preamble suppression option in order to
improve the error recovery capabilities. If an MDIO client device becomes
mis-aligned within the frame for some reason, it is much less likely to spot the
error if preamble suppression was allowed since the ST code is no longer
restricted to being '01'.
Regards
Ed
"Ben Brown" <bbrown@xxxxxxxx> on 20/09/2000 12:49:24
Sent by: "Ben Brown" <bbrown@xxxxxxxx>
To: "802.3ae" <stds-802-3-hssg@xxxxxxxx>
cc: (Edward Turner/GB/3Com)
Subject: Clause 33 comments
Ed,
Just a few comments from reading clause 33:
33.3.1.1.1 - page 69, line 48
While the reset process is not yet complete, the PMA/PMD is
not required to accept a write transaction to the control
register. Why is this limited to the control register? Why
aren't all the registers included?
33.3.3.2 - pages 80&81
Should we add a de-skew/lane alignment bit to this
register?
33.3.5 - page 84
When the address is 65535 and the access is a
post_xxx_increment, is the next address 0?
33.3.5.2 - page 85
Does this protocol support preamble suppression?
Ben
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