Re: Xaui jitter tolerance
Ali, to calculate the frequency change required for sinusoidal jitter:
multiply
PI * Jitter(in UIp-p) * Modulation Frequency(in Hz)
The result is frequency in Hz p-p which can be converted to ppm.
-Paul Wilson
Nortel Networks
-----Original Message-----
From: Ali Ghiasi <aghiasi@xxxxxxxxxxxxx>
To: Mike Jenkins <jenkins@xxxxxxxx>; 'richard_dugan@xxxxxxxxxxx'
<richard_dugan@xxxxxxxxxxx>
Cc: stds-802-3-hssg@xxxxxxxx <stds-802-3-hssg@xxxxxxxx>; Ali Ghiasi
<aghiasi@xxxxxxxxxxxxx>
Date: Thursday, November 30, 2000 4:52 AM
Subject: Re: Xaui jitter tolerance
HI
As Rihcard and Ed mentioned most SerDes have BW at least 3 time higher
as given by baudrate/1667. Increasing the corner frequency higher will
help transmitter with possible clock and PS noise to pass the jitter
specifications. Mike is also correct if we increase the corner
frequency significantly then we will violate +/- 100 PPM clock
specifications.
The current baudrate/1667 template fits under the +/-100 PPM
jitter assuming square wave and the jitter will change instantaneously
from min to max, which is rare. There might be some room to
increase the corner frequency and still not violate the +/- 100PPM.
Thanks,
Ali Ghiasi
Broadcom
Mike Jenkins wrote:
>
> Richard, Ed,
>
> I disagree with the proposal to increase the jitter corner frequency
> higher than baudrate/1667. First, the number 1667 is tied to the
> assumed +/-100 ppm reference frequency tolerance. I can't say it's
> an inviolable law of physics, but 1667 does make sense. (I'll try
> to dig up the explanation, if you want it.)
>
> Second, tracking jitter isn't always a good idea. One Fibre Channel
> jitter test pattern, CJTPAT, is designed to shift edges late, then
> early, repetitively. If the RX follows, it's jitter tolerance is
> reduced compared to averaging out this input jitter and keeping the
> sampling position fixed.
>
> If you would like more feedback on your proposal, I would suggest also
> posting it to the Fibre Channel phy layer reflector, t11_2@xxxxxxxxxxxx
>
> Regards,
> Mike
>
> Ed Grivna wrote:
> >
> > Hi Richard,
> >
> > I agree with your viewpoint. Many/most RX PLLs for this speed have
> > BW in the 10+ MHz range, which is what you want to allow fast pull-in
> > and tracking of jitter in high noise environments. The low BW is
> > generally a carry over from SONET environments where the
> > repeater functions (and the jitter gain in some parts of the PLL
transfer
> > function) can cause problems. As far qas I know, these implementations
> > are all re-timed to a local reference so jitter gain is not an issue.
> >
> > Regards,
> >
> > Ed Grivna
> > Cypress Semiconductor
> >
> > > Since XAUI jitter will likely be addressed in a separate meeting at
Austin,
> > > I would like to raise the issue of modifying the jitter tolerance
frequency
> > > "break point" from the standard baudrate/1667 (used in MJS) to
something
> > > significantly higher.
> > >
> > > For Xaui, the baudrate/1667 would give us a tolerance break point at
1.875
> > > MHz. My feeling is that there is nothing magical about the
baudrate/1667
> > > and that it doesn't accurately reflect typical receiver operation in
today's
> > > monolithic PLL's. (Perhaps in early telecom days SAW filter
applications
> > > required this, but today's receiver designs (at least in XAUI) will
not be
> > > using such costly techniques.) Moving the jitter tolerance break
point out
> > > to ~5 MHz or so would allow us to track more of the jitter components
and
> > > perhaps even make the Tx design easier (smaller capacitors, etc.).
> > >
> > > Soo, would there be any objections to moving the tolerance break point
out?
> > > I'd like to get some feedback on this before the Austin meeting if
> > > possible.
> > >
> > > - Richard Dugan
>
> --
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> Mike Jenkins Phone: 408.433.7901 _____
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